The study focuses on the optical and electrical properties of Tungsten Ditelluride (WTe2), a type II Weyl semimetal, as well as the influence of its self-limiting oxide (SLO) layer that forms during natural oxidation. WTe2 exhibits promising applications in photodetection and energy harvesting due to its unique gapless linear dispersion and Berry-field-enhanced nonlinear optical effects. However, surface oxidation poses a challenge as it degrades the performance of WTe2. By employing spectroscopic ellipsometry and Raman spectroscopy, the progression of the oxide layer’s thickness and its impact on the optical constants of WTe2 were examined. The results revealed a rapid increase in oxide thickness within the first 24 h, and it reached saturation at ∼10 nm after 45 h of atmospheric exposure. Electrical properties were explored using Kelvin Probe Force Microscopy, uncovering a modification in surface potential and Fermi level following oxidation. Additionally, a SLO/WTe2 heterojunction device exhibited a wide region of positive and negative coexisting photocurrent, highlighting the potential for logical operations in ambient air. Finally, the mechanism of operation of the device is discussed. The electrical and optical properties of the pristine, partially oxidized and fully oxidized WTe2 are analyzed using density functional theory calculations. It shows that the SLO layer has a significant effect on the optical and electronic properties, which is instructive for future wavelength-modulated device optoelectronic logic operations.@en

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

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Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

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The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

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Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency (f_ SRF) and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)-(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the f_ SRF of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and Rrm DSRF. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.

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Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

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With the advancement of power electronics, aluminum-clad copper thick bonding wires have garnered attentions due to superior electrical and thermal properties, making them well-suited for high-temperature and high-current applications. However, the impact remains unveiled of whether the growth of intermetallic compounds (IMCs) at the bonding interface presents critical challenges to the reliability of wedge wire bonds. Therefore, it is necessary to investigate the evolution behavior of Cu/Al IMCs in Al-clad copper wires. In this study, Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) were firstly employed to characterize the phase composition and growth behavior of Cu/Al intermetallic compounds (IMCs) at two distinct interfaces—the bonding interface and the core-shell interface—under various annealing conditions during high-temperature storage (HTS) tests, revealing a parabolic relationship between aging time and IMCs thickness. Subsequently, shear and pull tests of Al-clad copper bond wires were conducted to evaluate the bonding strength under different aging conditions, clarifying the correlation between various failure modes of the bonds and the evolution of IMCs at the bi-interfaces of this novel composite across different aging stages. Additionally, molecular dynamics (MD) simulations were employed to explore the diffusion behavior of Cu and Al atoms. It revealed that polycrystalline structures enhanced the mutual diffusion at the interface, with copper serving as the predominant element in the interdiffusion process. In conclusion, this study integrates experimental and numerical approaches to elucidate the growth mechanisms of Cu/Al intermetallic compounds and their effects on reliability, providing valuable guidance for optimizing the performance of composite bonding wires in high-temperature power device applications.

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The demand for accurate temperature sensing in extreme temperatures is increasing. Traditional silicon-based integrated temperature sensors usually cannot survive above 200 °C. Many researchers have started to focus on semiconductors with a large bandgap. Among them, silicon carbide (SiC) is the most promising one. Nevertheless, most reported SiC sensors are in the form of discrete components and are not compatible with integrated electronics. In this work, we demonstrate an open 4H-SiC CMOS technology, and the fabrication steps are detailed. The temperature sensing elements in this technology, including resistors based on different implanted layers and MOSFETs, are characterized up to 600 °C. At room temperature, the resistive-based elements demonstrate large negative temperature coefficients of resistance (TCRs). With increasing temperature, the TCR starts to decrease and even becomes positive. The TCR change is due to the interplay between increasing dopant ionization rate and decreasing mobility as a function of temperature. The resistance change with temperature fits well into the Steinhart-Hart model and second-order polynomial equation. The p-type diode-connected MOSFET has a sensitivity of 4.35 mV/°C with a good linearity. The nMOS-based sensor has a maximum sensitivity of -9.24 mV/°C but a compromised linearity. The characterization of these sensing elements provides important results for potential users who will work on SiC integrated temperature sensing with this technology.

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The significance of wafer bonding is fundamental to the progression of electronic systems. Common fabrication techniques for Cu pillars play a crucial role in establishing resilient and efficient interconnects within semiconductor devices. It is imperative to explore the potential of nano-copper as an alternative material to overcome limitations associated with conventional copper. The use of nano copper paste in manufacturing has the potential to simplify the process, potentially reducing the number of steps compared to conventional methods. This study delves into the intricacies of wafer-level packaging (WLP), with a particular focus on hybrid bonding processes utilizing nanocopper sintering. Through the application of Finite Element Method (FEM) simulations, we investigate the stress distribution and thermal dynamics inherent in the sintering and hybrid bonding of both bulk copper and nanocopper materials. Our findings illuminate the superior mechanical and thermal properties of nanocopper, which contribute to reduced stress concentrations and enhanced mechanical integrity in semiconductor packaging. The research highlights the pivotal role of nanocopper sintering in advancing WLP technologies, offering insights into optimizing sintering and bonding parameters for improved device reliability and performance.@en

Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller Rb and more difficult to active parasitic BJT.@en

During operation in environments containing hydrogen sulfide (H₂S), such as in offshore and coastal environments, sintered nanoCu in power electronics is susceptible to degradation caused by corrosion. In this study, experimental and molecular dynamics (MD) simulation analyses were conducted to investigate the evolution and mechanism of H₂S-induced corrosion of sintered nanoCu, and bulk Cu was used as the reference. The following results are obtained: (1) Both sintered nanoCu and bulk Cu reacted with O₂ prior to reacting with H₂S, forming Cu₂O, Cu₂S, CuO, and CuS. In addition, sintered nanoCu exhibited more severe corrosion. (2) For both sintered nanoCu and bulk Cu, H₂S-induced corrosion resulted in the deterioration of electrical, thermal, and mechanical properties, and sintered nanoCu experienced a greater extent of deterioration. (3) As was ascertained through Reactive Force Field (ReaxFF) MD simulations, the penetration of H₂S and O₂ combined with the upward migration of Cu resulted in the formation of a corrosion film. In addition, compared to bulk Cu, the H₂S and O₂ penetration in the sintered nanoCu structure was observed to occur to a greater depth, accounting for the more pronounced performance degradation.

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During the operation of an LED array, its thermal and optical performances are always not equal to the superposition of the individual LED's characteristics because of a significant thermal coupling effect between the arrays. Based on this, this paper proposes an electrical–photo-thermal model, with considering both junction temperature and luminous flux, to predict the both the thermal and optical performances of LED arrays operated under different currents, case temperatures, and lighting methods. The junction temperature and luminous flux of a single LED operating under different driving currents and case temperature conditions are firstly collected to establish the luminous flux response surface model of a single chip. Then it is used to predict the luminous flux of an array, whose junction temperature is predicted using both thermal coupling matrix (TCM) and numerical models. Experiments verify the luminous flux of the LED array under different operation conditions and show that the proposed electrical–photo-thermal modeling can be used to predict the thermal and optical parameters of LED arrays with 95 % accuracy. Thus, it is effective for the fast prediction of the junction temperature and luminous flux of large LED systems with array structures, i.e. intelligent automotive lightings and displays.

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In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided Design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.

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The power semiconductor joining technology through sintering of copper nanoparticles is well-suited for die attachment in wide bandgap (WBG) semiconductors, offering high electrical, thermal, and mechanical performances. However, sintered nanocopper will be prone to degradation resulting from corrosion in sulfur-containing corrosive environments such as offshore areas. In this study, experiments, including aging test and corrosion characterization, and simulations based on density functional theory (DFT) studies were conducted to explore the corrosion behavior and mechanism of elemental sulfur (S₈) and hydrogen sulfide (H₂S) on sintered nanocopper. The experimental results indicated that loose corrosion products were observed on the sintered nanocopper during the ageing process involving S₈, and compact layered corrosion products formed during the ageing process involving H₂S. Furthermore, similar corrosion product compositions (Cu₂O, Cu₂S, CuO, CuS, and potentially Cu₂SO₄ or CuSO₄) were observed in both the S₈- and H₂S-ageing processes. However, the S₈-ageing process exhibited more noticeable corrosion penetration. This was explained in simulations results: the unsaturated Cu sites on the oxide layer [Cu₂O(1 1 1)] of the sintered nanocopper could adsorb both H₂S and S₈, while the saturated Cu sites only exhibited the potential to adsorb S₈.

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A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

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This work addresses a novel technique for selecting the best process parameters for the 4H–SiC epitaxial layer in a horizontal hot-wall chemical vapor reactor using a transient multi-physical (thermal-fluid-chemical) simulation model and combined with a machine-learning model. An experiment was performed to validate the feasibility of the numerical model. Secondly, a single-factor analysis was conducted to investigate the effects of process parameters, including the deposition temperature, inlet-flow volume, rotational speed of the susceptor, and cavity pressure, on the quality of the 4H–SiC epitaxial layer. Finally, a machine learning algorithm, the ant colony optimization-back propagation neural network (ACO–BPNN), was employed to develop the input/output model and optimize process parameters for obtaining a high-quality epitaxial layer and reducing the optimization cycle and costs. Notably, the optimized process was validated by real experiments, where the error between calculation and experiment is 4.03 % for deposition rate and 0.49 % for coefficient of variation, respectively. The results highlight the model as reliable and lay the foundation for the CVD growth of the 4H–SiC epitaxial layer.

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Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

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Copper sintering has gained great attention as a die-attach technology for power electronics because of its potential cost effectiveness and high reliability under harsh working conditions. However, the mechanism of how the intrinsic pores within such sintered joints influence the thermal and electrical properties still needs further investigation. The evolution of pores within such sintered joints is difficult for in-situ observation during the sintering process and reliability tests, while the porosity level greatly affects the thermal and electrical properties. In this work, four two-dimensional (2D) models with various random pore structures were established based on the Quartet Structure Generation Set (QSGS) algorithm. Then, finite element method (FEM) simulations were conducted to simulate the heat and current conduction in the sintered materials. Subsequently, the distribution of temperature as well as the electric potential in the porous sintered materials were further discussed. Lastly, both the thermal and the electrical conductivities were calculated, followed by a concluded parabolic relationship of thermal and electrical conductivities with the porosity. These findings offer insights into optimizing and predicting copper sintered joint performance and accelerate the wide application of copper sintering.

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Silicon carbide (SiC) MOSFETs, as leading wide bandgap semiconductor devices, exhibit superior stability and reliability under high-temperature, high-switching frequencies, and high-power density operational conditions. SiC MOSFET with fan-out panel-level packaging (FOPLP) utilizes a redistribution layer (RDL) to substitute bonding wires, achieving low thermal resistance, electrical resistance, and parasitic inductance. This study proposes an optimal design strategy for SiC MOSFET FOPLP, considering parasitic inductance suppression, heat dissipation, thermal-mechanical reliability, and insulation enhancements. First, we establish the parasitic inductance, heat transfer network, and thermomechanical stress physical analytical models of SiC MOSFET FOPLP. Subsequently, the non-dominated sorting genetic algorithm (NSGA-II) and the improved multi-objective particle swarm optimization algorithm (MOPSO) are integrated to realize the co-optimization of parasitic inductance, thermal resistance, thermal stress, and electric field intensity distribution. Finally, we attain the optimal parameters of the SiC MOSFET FOPLP, i.e. chip thickness (x₁), solder thickness (x₂), RDL thickness (x₃), and chip side length (x₄) as 0.25 mm, 0.05 mm, 0.35 mm, and 6.00 mm, respectively. Additionally, according to comparison the MOPSO algorithm exhibits faster convergence and superior diversity than NAGA-II in the electrical-thermal-mechanical multiphysics co-optimization. Generally, the proposed physical analytical models combined with a multi-objective optimization method have a substantial guidance and forward-looking prospect on the design of SiC MOSFET FOPLP.

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Electromigration (EM) is a crucial failure mode in Aluminum (Al) interconnection wires those are widely used in high density semiconductor packaging. This study systematically investigated the influence of EM on the mechanical properties of Al interconnects via nanoindentation experiments and molecular dynamics (MD) simulations. The results are list as follows. (1) The indentation depth gradually increases with the increase in indentation load, resulting in a gradual increase and stabilization of the Young’s modulus and hardness of the structure. Within a specific range, the influence of the loading rate on the indentation depth and mechanical properties is relatively small. (2) The region where Young’s modulus of the interconnect decreases correlates with the location where EM-induced voids initiate. EM-induced voids have a direct impact on the material’s mechanical properties, particularly the decrease in Young’s modulus. (3) These EM-induced voids affect the nucleation and formation of dislocations. With the increase in void concentration and indentation depth, The generation and slip of dislocations increase as the void concentration and indentation depth increase, leading to a decrease in the material’s mechanical properties over time. This comprehensive findings expand the knowledge on mechanical behavior degradation of Al interconnects when EM failure occurs, providing a scientific basis for designing and optimizing high density semiconductor packaging.@en