Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency (f_ SRF) and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)-(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the f_ SRF of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and Rrm DSRF. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.

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Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic inductance (LS). Numerical calculation shows that the number of bond wire liftoffs will change the LS, which can be used as an effective bond wire damage precursor. Considering a power MOSFET as a two-port network, LS is accurately extracted from frequency domain impedance (Z−parameter) using a vector network analyzer under zero biasing conditions. Bond wire cutoff experiments are employed to validate the proposed approach for bond wire damage detection. The result shows that LS increases with the rising severity of bond wire faults, and even the slight fault shows a high sensitivity, which can be effectively used to quantify the number of bond wire liftoffs of discrete MOSFETs. Meanwhile, the source parasitic resistance (RS) extracted from the proposed two-port network measurement can be used for the bond wire damage detection of high switching frequency silicon carbide MOSFETs. This approach offers an effective quality screening technology for discrete MOSFETs without power on treatment.

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With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (R_DS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (R_D + R_S) during the quality degradation proceeding. This finding matches with the correlation established between R_{DS (on)} and R_D + R_S in theory. Meanwhile, source parasitic inductance (L_S) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.

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Silicon carbide (SiC) is a third-generation semiconductor material with many advantages, such as high thermal conductivity, high critical breakdown voltage, and high saturated electron drift velocity, which can increase the operating frequency of the power conversion system to more than 100kHz. In the high-frequency, the parasitic effect will significantly reduce the switching speed of the power devices, increase power consumption and influence the uniformity of current distribution. In this paper, we established the calculation nodes of each part of the SiC-MOSFET Half-bridge power module and used ANSYS Q3D software to extract the parasitic parameters. Die-Die, Die-DBC-1, Die-DBC-2 and hybrid interconnect package structures were designed to optimize the parasitic inductance. Simulation results indicated that the chip-DBC-1 structure can reduce the parasitic inductance about 30% compared with Chip-Chip structure and effectively control the uniformity of current density on two parallel diode chips (ΔLdiode <0.1%). In the meantime, an 3D model of partial bond wires broken were designed to get further insight into the variation of parasitic inductances. The correlation mechanism between the partial bond wires broken and inductance change of the D-S terminals current path was studied. The results showed that as the number of broken bond wires increases, the inductance of D-S terminals current path was increased gradually. Finally, by using two-port S-parameters measurement method to extract the inductances of the discrete power device, the experimental results indicated that when one or two bond wires were broken, the inductance of D-S terminals current path increased by 4.69% and 15.69%, respectively. Overview, a risk evaluation method for SiC power devices based on the variation of the parasitic parameters of the bond wire was established.@en

A novel silicone rubber elastic key (SREK) is proposed in this paper for surface mounting technology (SMT) applications. Effects of thermal reflowing stress on the mechanical properties of SMT-SREKs are investigated. The manufactured SMT-SREKs, which underwent various reflowing conditions in advance, are subjected to pressing force and fatigue pressing tests. Fatigue lifetime projection model and its predicted error are then assessed systematically. The thermal degradation of silicone rubber materials is illustrated through the dynamic mechanical analysis and the Fourier transform infrared spectroscopy experiments. The mechanical finite element modeling is also conducted to simulate the pressing process. The results show that the pressing force and tactility of the SMT-SREKs are strongly affected by the reflowing condition, which contributes to the degradation of the silicone rubber materials. During the fatigue pressing test, the change rate of tactility increases with the reflowing peak temperature ( T-{p} ) and is accelerated by the repeated reflowing process. Moreover, a linear model can precisely project the tactility before the fatigue pressing number of 2.0E+6 times, and the impact rate of T-{p} on tactility with the increasing fatigue pressing number can be predicted effectively by using a logarithm model.

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