Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace’s equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments.@en

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal-oxide-semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

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Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency (f_ SRF) and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)-(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the f_ SRF of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and Rrm DSRF. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.

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A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

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As the dimensions of interconnects in integrated circuits continue to shrink, an urgent need arises to understand the physical mechanism associated with electromigration. Using x-ray nanodiffraction, we analyzed the stresses in Blech-structured pure Cu lines subjected to different electromigration conditions. The results suggest that the measured residual stresses in the early stages of electromigration are related to relaxation of stresses caused by thermal expansion mismatch, while a developing current-induced stress leads to reductions in the residual stress after longer test times. These findings not only validate the feasibility of measuring stress in copper lines using nanodiffraction but also highlight the need for a further understanding, particularly through in situ electromigration experiments with x-ray nanodiffraction analysis.

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In this article, we provide a comprehensive review of defect formation at the atomic level in interfaces and gate oxides, focusing on two primary defect types: interface traps and oxide traps. We summarize the current theoretical models and experimental observations related to these intrinsic defects, as they critically impact device performance and reliability. By integrating theoretical insights with experimental data, this review provides a thorough understanding of the atomic-scale interactions that govern defect formation.

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Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

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This work addresses a novel technique for selecting the best process parameters for the 4H–SiC epitaxial layer in a horizontal hot-wall chemical vapor reactor using a transient multi-physical (thermal-fluid-chemical) simulation model and combined with a machine-learning model. An experiment was performed to validate the feasibility of the numerical model. Secondly, a single-factor analysis was conducted to investigate the effects of process parameters, including the deposition temperature, inlet-flow volume, rotational speed of the susceptor, and cavity pressure, on the quality of the 4H–SiC epitaxial layer. Finally, a machine learning algorithm, the ant colony optimization-back propagation neural network (ACO–BPNN), was employed to develop the input/output model and optimize process parameters for obtaining a high-quality epitaxial layer and reducing the optimization cycle and costs. Notably, the optimized process was validated by real experiments, where the error between calculation and experiment is 4.03 % for deposition rate and 0.49 % for coefficient of variation, respectively. The results highlight the model as reliable and lay the foundation for the CVD growth of the 4H–SiC epitaxial layer.

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Digital Twins (DT) play a key role in Industry 4.0 applications, and the technology is in the process of being mature. Since its conceptualisation, it has been heavily contextualised and often misinterpreted as being merely a virtual model. Thus, it is crucial to define it clearly and have a deeper understanding of its architecture, workflow, and implementation scales. This paper reviews the notion of a Digital Twin represented in the literature and analyses different kinds of descriptions, including several definitions and architectural models. A new fit-for-all definition is proposed which describes the underlying technology without being context-specific and also overcomes the pitfalls of the existing generalised definitions. In addition, the existing three-dimensional and five-dimensional models of the DT architecture and their characteristic features are analysed. A new simplified two-branched model of DT is introduced, which retains a clear separation between the real and virtual spaces and outlines the latter based on the two key modelling approaches. This model is then extended for condition monitoring of electronic components and systems, and a hybrid approach to Prognostics and Health Management (PHM) is further elaborated on. The proposed framework, enabled by the two-branched Digital Twin model, combines the physics-of-degradation and data-driven approaches and empowers the next generation of reliability assessment methods. Finally, the benefits, challenges, and outlook of the proposed approach are also discussed.@en

This study demonstrates a breakdown analysis of the dynamics of a liquid crystal elastomer (LCE) including quality check, geometric measurement, thermal characterization, and comparison of heat- and light-induced contractions. A blue light-responsive acrylate side chain LCE with 1% azobenzene dye was characterized. From a classical viewpoint, photo-thermal contraction is considered a dominating effect, while direct photo-mechanical deformation can be neglected due to a low dye percentage. However, the findings of this research suggest that a low percentage of azobenzene dye does not necessarily lead to heat-dominating dynamics of LCE. This phenomenon has not yet been quantitatively studied before. The approach reported in this Letter can potentially be used to extract the data to improve the dynamics models of light-driven LCEs.

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Model order reduction techniques are developed and utilized to make numerical simulations more efficient. The use of Reduce Order Models (ROM) also enables data exchange with external parties without disclosing the sensitive information present in a Full-Order Model (FOM). It is crucial to optimize for both the efficiency and accuracy of a ROM to keep a minimal deviation from the FOM. The complexity of a ROM-based simulation depends on the definition of the ROM as well as its connection with the remaining FOM. This paper investigates the effect of different ROM-FOM interface definitions for a test case consisting of an electronic package-on-PCB assembly. A virtual Design of Experiments (DoE) was carried out with a total of 41 cases considering three different locations and up to four different constraint equations for the ROM-FOM interface. The effect on the accuracy and time-efficiency of the ROM-based thermomechanical simulations are compared with respect to the full Finite Element (FE) model. The deformable configuration for the interface generally showed the most accurate results, while the rigid configuration was the most efficient across the board. The beam configuration did not always follow an expected trend based on the order of elasticity values of the assigned materials. Based on the deformation results and the time associated with ROM generation and use-pass, multiple optimal solutions from the DoE are discussed.@en

Abstract-Prognostic monitoring of Power QFN packages with four distinct silver pastes, each varying in material composition (pure-Ag and resin-reinforced hybrid-Ag) and sintering processes (pressure-assisted and pressureless), was investigated in this study. The PQFN packages with silver sintered die-attach materials were subjected to thermal cycling tests (-55 to 150°C), and the performance degradation was evaluated based on the following metrics: (i.) Electrical on-state resistance R_DS monitored periodically at specific thermal cycling intervals, and (ii.) Transient thermal impedance Z_th(t=0.1 s) monitored online during thermal cycling. These measurements were further validated using acoustic microscopy imaging and cross-sectional inspection. The pressureless Ag-sintering material demonstrated comparable performance to pressure-assisted Ag-sintering, with a dense microstructure, and consistent electrical and stable thermal performance. Whereas the pressureless resin-reinforced hybrid-Ag material exhibited degradation with a relative increase of ~33% in R_DSon, ~38% in Z_th(t=0.1 s), and ~67% delamination of the die-attach interface over 1000 cycles. These findings suggest that pressureless Ag-sintering may offer a viable alternative to pressure-assisted methods for Pb-free die-attachments, while resin-reinforced hybrid-Ag requires further development for improved thermo-mechanical reliability.

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Driven by the increasing demand for high-power systems, ceramic substrates have received more attention for handling higher power density. Warpage in active metal brazed (AMB) ceramic substrate becomes a critical issue as it can deteriorate the reliability performance. This study comprises three phases, including investigation of the cause of the warpage, validation of the proposed model, and optimization for effective warpage management. At first, the coefficient of thermal expansion (CTE) and yield strength of the copper (Cu) layer in AMB were characterized and adopted in a two-dimensional (2D) finite element model. The evolution of simulated strain and moments revealed the cause of the warpage during the manufacturing processes. Furthermore, the 2D model was extended to a three-dimensional (3D) model. The finite element method (FEM) and experiments were conducted on different heat treatment conditions for 3D model validation. The validated 3D model was applied to carry out a design of experiments (DoEs) for design optimization to reduce the warpage. Consequently, the factor analysis in DoEs was demonstrated by different pattern designs using subtractive milling techniques.@en

The COVID-19 pandemic has highlighted the need for rapid and sensitive detection of SARS-CoV-2. Here, we report an ultrasensitive SARS-CoV-2 immunosensor by integration of an AlGaN/GaN high-electron-mobility transistor (HEMT) and anti-SARS-CoV-2 spike protein antibody. The AlGaN/GaN HEMT immunosensor has demonstrated the capability to detect SARS-CoV-2 spike proteins at an impressively low concentration of 10−22 M. The sensor was also applied to pseudoviruses and SARS-CoV-2 ΔN virions that display the Spike proteins with a single virion particle sensitivity. These features validate the potential of AlGaN/GaN HEMT biosensors for point of care tests targeting SARS-CoV-2. This research not only provides the first HEMT biosensing platform for ultrasensitive and label-free detection of SARS-CoV-2.@en

Silver sintering offers a promising landscape for Pb-free die attachment in electronics packaging. However, the sintered interface properties are highly process-dependent and deviate from bulk silver properties. Conventional measurement methods do not adequately capture the die-attach application geometry. Hence, this study introduces a novel methodology for characterizing thin bond-line interfaces with high-conductive materials. The transient heat flux impedance ΔZth(t, Δx) was measured between two thermally sensitive devices interconnected using pressureless Ag-sintering material. A correction factor was derived, based on thermal half-space principles, to account for non-uniform heat spreading over the die-attach interface. Experimental findings estimate an effective conductivity of ∼115W/mk for the pressureless Ag-sintered interface. The measurement results were validated by measuring a SAC305 soldered interface, which exhibited ∼55 W/mK, and a non-conductive epoxy interface of ∼2.5 W/mK. Voids on the die-attach layer, resulting from material processing, were identified to influence the interface thermal behavior. An uncertainty analysis was further discussed, emphasizing equipment tolerances, measurement sensitivity, and geometrical and thermal anisotropies. The article concludes with a comparative summary of the proposed methodology against conventional methods, highlighting differences in working principle, thickness range, measurement parameters, and their advantages and limitations.@en

Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

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The power semiconductor joining technology through sintering of copper nanoparticles is well-suited for die attachment in wide bandgap (WBG) semiconductors, offering high electrical, thermal, and mechanical performances. However, sintered nanocopper will be prone to degradation resulting from corrosion in sulfur-containing corrosive environments such as offshore areas. In this study, experiments, including aging test and corrosion characterization, and simulations based on density functional theory (DFT) studies were conducted to explore the corrosion behavior and mechanism of elemental sulfur (S₈) and hydrogen sulfide (H₂S) on sintered nanocopper. The experimental results indicated that loose corrosion products were observed on the sintered nanocopper during the ageing process involving S₈, and compact layered corrosion products formed during the ageing process involving H₂S. Furthermore, similar corrosion product compositions (Cu₂O, Cu₂S, CuO, CuS, and potentially Cu₂SO₄ or CuSO₄) were observed in both the S₈- and H₂S-ageing processes. However, the S₈-ageing process exhibited more noticeable corrosion penetration. This was explained in simulations results: the unsaturated Cu sites on the oxide layer [Cu₂O(1 1 1)] of the sintered nanocopper could adsorb both H₂S and S₈, while the saturated Cu sites only exhibited the potential to adsorb S₈.

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The demand for accurate temperature sensing in extreme temperatures is increasing. Traditional silicon-based integrated temperature sensors usually cannot survive above 200 °C. Many researchers have started to focus on semiconductors with a large bandgap. Among them, silicon carbide (SiC) is the most promising one. Nevertheless, most reported SiC sensors are in the form of discrete components and are not compatible with integrated electronics. In this work, we demonstrate an open 4H-SiC CMOS technology, and the fabrication steps are detailed. The temperature sensing elements in this technology, including resistors based on different implanted layers and MOSFETs, are characterized up to 600 °C. At room temperature, the resistive-based elements demonstrate large negative temperature coefficients of resistance (TCRs). With increasing temperature, the TCR starts to decrease and even becomes positive. The TCR change is due to the interplay between increasing dopant ionization rate and decreasing mobility as a function of temperature. The resistance change with temperature fits well into the Steinhart-Hart model and second-order polynomial equation. The p-type diode-connected MOSFET has a sensitivity of 4.35 mV/°C with a good linearity. The nMOS-based sensor has a maximum sensitivity of -9.24 mV/°C but a compromised linearity. The characterization of these sensing elements provides important results for potential users who will work on SiC integrated temperature sensing with this technology.

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Power electronic modules have undergone a remarkable transition in terms of power density, temperature, and performance due to the shift from Si to WBG (Wide bandgap) semiconductors. WBG semiconductors with their high switching speed, high breakdown voltage and higher operation temperature outperform their Si counterparts. However, the current power packaging technologies are not sufficient to benefit from the superior properties of these WBG devices. For Si power electronic packaging, the traditional 500 μm Al wire bonding as top-side interconnection can carry a maximum current of 10 A which can be increased by parallel connections. However, the need for a higher current carrying capacity with a lower feature size is desirable for WBG devices. As a result, the conventional wire-bonding technology hinders these devices from reaching their full potential due to parasitics, heat dissipation, and reliability issues. To address these challenges, several wire bondless interconnection technologies have been proposed and developed. Among these technologies, a new alternative technology has been recently introduced by our group in which wire bonds are being replaced by printed Cu paste interconnects known as 'Cu sinterconnects®', So far, sinterconnects® have been only integrated into large IGBT power module packages where their efficiency has been proven. In this study, sinterconnects have been further optimized to be integrated into GaN-based discrete device discrete packages with fine feature sizes. The packaged GaN devices with fine-sinterconnects® were further characterized and compared with the standard wire-bonded GaN packages.

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This report demonstrates an innovative method to achieve large scale 20 μm pitch Cu-Cu direct bonding, utilizing lithographic stencil printing to transfer small-sized nano-copper (CuNPs) paste and employs a thermocompression method for CuNPs sintering to establish interconnections between copper-pillars and CuNPs bumps. Shear tests were conducted to characterize the bonding strength. High-throughput 20 μm pitch copper-to-copper direct bonding enables lower annealing temperatures for bulk-Cu to bulk-Cu bonding. Lithographic stencil printing is used to transfer the CuNPs paste, followed by sintering of the nanoparticles to establish interconnections. Shear tests and cross-section SEM were conducted to characterize the bonding strength and quality.

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