This paper compares and evaluates the single pulse short-circuit robustness of SiC MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.@en

The study focuses on the optical and electrical properties of Tungsten Ditelluride (WTe2), a type II Weyl semimetal, as well as the influence of its self-limiting oxide (SLO) layer that forms during natural oxidation. WTe2 exhibits promising applications in photodetection and energy harvesting due to its unique gapless linear dispersion and Berry-field-enhanced nonlinear optical effects. However, surface oxidation poses a challenge as it degrades the performance of WTe2. By employing spectroscopic ellipsometry and Raman spectroscopy, the progression of the oxide layer’s thickness and its impact on the optical constants of WTe2 were examined. The results revealed a rapid increase in oxide thickness within the first 24 h, and it reached saturation at ∼10 nm after 45 h of atmospheric exposure. Electrical properties were explored using Kelvin Probe Force Microscopy, uncovering a modification in surface potential and Fermi level following oxidation. Additionally, a SLO/WTe2 heterojunction device exhibited a wide region of positive and negative coexisting photocurrent, highlighting the potential for logical operations in ambient air. Finally, the mechanism of operation of the device is discussed. The electrical and optical properties of the pristine, partially oxidized and fully oxidized WTe2 are analyzed using density functional theory calculations. It shows that the SLO layer has a significant effect on the optical and electronic properties, which is instructive for future wavelength-modulated device optoelectronic logic operations.@en

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

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This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

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Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

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Driven by the need for improved quality, energy efficiency, and visual innovation, display technology has evolved from CRT to Mini LED. However, the transfer process in Mini LED assembly poses challenges in precision. This study addressed the displacement issue during the transfer process by investigating the synergistic effects of solder and functional organic chemicals. Through the Mini LED assembly process, with the Mini LED size measuring 150 μm (length) ∗ 100 μm (width) ∗ 70 μm (thickness), polyamide was identified as a facilitator for precise alignment, which enhanced self-alignment capabilities by 68.8 % and improved the accuracy on self-aligned distance from 12.5 μm to 21.1 μm in Mini LED packaging. Through the powder coalescence approach, further extensive analysis using XPS, SEM, FTIR, and DSC reveals the synergistic effects. It supports the proposed three-dimensional polyamide-tin ion coordination interfacial network construction mechanism that facilitates solder-to-solder self-alignment and coalescence. This study provides insight into such a polymer-metal ion 3D coordination network for Mini LED precise alignment, which is promising for mass production.@en

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal-oxide-semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

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The COVID-19 pandemic has highlighted the need for rapid and sensitive detection of SARS-CoV-2. Here, we report an ultrasensitive SARS-CoV-2 immunosensor by integration of an AlGaN/GaN high-electron-mobility transistor (HEMT) and anti-SARS-CoV-2 spike protein antibody. The AlGaN/GaN HEMT immunosensor has demonstrated the capability to detect SARS-CoV-2 spike proteins at an impressively low concentration of 10−22 M. The sensor was also applied to pseudoviruses and SARS-CoV-2 ΔN virions that display the Spike proteins with a single virion particle sensitivity. These features validate the potential of AlGaN/GaN HEMT biosensors for point of care tests targeting SARS-CoV-2. This research not only provides the first HEMT biosensing platform for ultrasensitive and label-free detection of SARS-CoV-2.@en

This work addresses a novel technique for selecting the best process parameters for the 4H–SiC epitaxial layer in a horizontal hot-wall chemical vapor reactor using a transient multi-physical (thermal-fluid-chemical) simulation model and combined with a machine-learning model. An experiment was performed to validate the feasibility of the numerical model. Secondly, a single-factor analysis was conducted to investigate the effects of process parameters, including the deposition temperature, inlet-flow volume, rotational speed of the susceptor, and cavity pressure, on the quality of the 4H–SiC epitaxial layer. Finally, a machine learning algorithm, the ant colony optimization-back propagation neural network (ACO–BPNN), was employed to develop the input/output model and optimize process parameters for obtaining a high-quality epitaxial layer and reducing the optimization cycle and costs. Notably, the optimized process was validated by real experiments, where the error between calculation and experiment is 4.03 % for deposition rate and 0.49 % for coefficient of variation, respectively. The results highlight the model as reliable and lay the foundation for the CVD growth of the 4H–SiC epitaxial layer.

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Ionic FETs have enormous potential for energy conversion, sensing, and ionic circuits due to their efficient regulation of the nanochannel. Here ionic FETs based on single-crystal silicon nanopores and the rectification of the fabricated devices are studied. The electrical characterization results demonstrated that since the silicon-based nanopores have the advantage of modulating the surface charge due to their semiconductor nature and benefitting from the effective 3D gating effect on the nanochannel, the magnitude and polarity of surface charge can be modulated by the gate voltage. The rectification effect can be adjusted by applying a certain voltage and fulfilling a transition between anion selectivity and cation selectivity when the surface charge polarity is reversed. Moreover, current–voltage characteristics of the reported ionic FET can be switched between ohmic and diode-like regimes. The proposed ionic FETs supply a novel platform to study the ionic properties and have great potential to be applied in large-scale ionic circuits due to their excellent performance. Finally, simulation results prove the surface charge modulated by the gate voltage determines the magnitude and direction of rectification, which is consistent with the reported experiment result.

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Solder fatigue is a key failure mode in the electronic industry. Monitoring the actual degradation of the solder under real-time conditions in any application would be extremely beneficial. In this chapter, we describe the combination of experimental material characterization with numerical finite element (FE) simulations to obtain a prognostics and health monitoring (PHM) methodology for LED drivers used in outdoor lighting applications. Experimental characterization of a new type of solder is described. A FE model is created of a typical component in electronic drivers. The calculated damage level and the collected life data correlate together and form a model for predicting the lifetime of the drivers at certain user condition. The developed PHM methodology helps in identifying and reporting the failure of the driver in real time or can be used for predicting the actual remaining useful life (RUL).

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The significance of wafer bonding is fundamental to the progression of electronic systems. Common fabrication techniques for Cu pillars play a crucial role in establishing resilient and efficient interconnects within semiconductor devices. It is imperative to explore the potential of nano-copper as an alternative material to overcome limitations associated with conventional copper. The use of nano copper paste in manufacturing has the potential to simplify the process, potentially reducing the number of steps compared to conventional methods. This study delves into the intricacies of wafer-level packaging (WLP), with a particular focus on hybrid bonding processes utilizing nanocopper sintering. Through the application of Finite Element Method (FEM) simulations, we investigate the stress distribution and thermal dynamics inherent in the sintering and hybrid bonding of both bulk copper and nanocopper materials. Our findings illuminate the superior mechanical and thermal properties of nanocopper, which contribute to reduced stress concentrations and enhanced mechanical integrity in semiconductor packaging. The research highlights the pivotal role of nanocopper sintering in advancing WLP technologies, offering insights into optimizing sintering and bonding parameters for improved device reliability and performance.@en

MAlSiN₃:Eu²⁺ (M = Ca, Sr) is commonly used in high-power phosphor-converted white-light-emitting diodes and laser diodes to promote their color-rendering index. However, the wide application of this phosphor is limited by the degradation of its luminescent properties in high-temperature, high-humidity, and high-sulfur-content environment. Here, the degradation mechanism of the (Sr,Ca)AlSiN₃:Eu²⁺ (SCASN) red phosphor under thermal-moisture-sulfur coupling conditions is investigated. Furthermore, by performing first-principles calculations, the hydrolysis mechanism on an atomic scale is assessed. The adsorption energy (E_ads) and charge transfer (ΔQ) results showed that H₂O chemically adsorbed on the (0 1 0), (3 1 0), and (0 0 1) surfaces of the CaAlSiN₃ (CASN) host lattice. The energy barrier for H₂O dissociation is only 29.73 kJ mol⁻¹ on the CASN (0 1 0) surface, indicating a high dissociation probability. The formation of NH₃, Ca(OH)₂, and CaAl₂Si₂O₈ is confirmed by H⁺ tended to combine with surface N atoms, while OH⁻ combined with the surface Al/Si or Ca atoms. Moreover, ab initio molecular dynamics simulations were performed to further understand the hydrolysis process. This work offers a guidance on the design and applications of luminescent materials in LED packages with higher reliability and stability requirements in harsh environment.

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With the increase in voltage level and current capacity of the insulated gate bipolar transistor (IGBT), the avalanche effect has become an important factor limiting the safe operating area (SOA) of the device. The hole injection into the p/n junction on the backside of the IGBT after avalanche is the main feature that distinguishes the avalanche effect from other devices. In this paper, the avalanche breakdown characteristics of IGBT and the nature of current filament are investigated using theoretical analysis and numerical simulation, and the underlying physical mechanism controlling the nature of current filaments is revealed. The results show that the hole injection on the backside of the IGBT leads to an additional negative differential resistance (NDR) branch on the avalanche breakdown curve. The device’s common-base current gain, αpnp, is a crucial factor in determining the current filament. As αpnp increases, the avalanche-induced current filament becomes stronger and slower, resulting in weaker avalanche robustness of the device.@en

Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150°C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (i.e., the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150°C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation.@en

Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller Rb and more difficult to active parasitic BJT.@en

Copper sintering has gained great attention as a die-attach technology for power electronics because of its potential cost effectiveness and high reliability under harsh working conditions. However, the mechanism of how the intrinsic pores within such sintered joints influence the thermal and electrical properties still needs further investigation. The evolution of pores within such sintered joints is difficult for in-situ observation during the sintering process and reliability tests, while the porosity level greatly affects the thermal and electrical properties. In this work, four two-dimensional (2D) models with various random pore structures were established based on the Quartet Structure Generation Set (QSGS) algorithm. Then, finite element method (FEM) simulations were conducted to simulate the heat and current conduction in the sintered materials. Subsequently, the distribution of temperature as well as the electric potential in the porous sintered materials were further discussed. Lastly, both the thermal and the electrical conductivities were calculated, followed by a concluded parabolic relationship of thermal and electrical conductivities with the porosity. These findings offer insights into optimizing and predicting copper sintered joint performance and accelerate the wide application of copper sintering.

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In this study, a convenient chitosan oligosaccharide laser lithograph (COSLL) technology was developed to fabricate laser-induced graphene (LIG) electrodes and flexible on-chip microsupercapacitors (MSCs). With a simple one-step CO₂ laser, the pyrolysis of a chitosan oligosaccharide (COS) and in situ welding of the generated LIGs to engineering plastic substrates are achieved simultaneously. The resulting LIG products display a hierarchical porous architecture, excellent electrical conductivity (6.3 Ω sq^-1), and superhydrophilic properties, making them ideal electrode materials for MSCs. The pyrolysis-welding coupled mechanism is deeply discussed through cross-sectional analyses and finite element simulations. The MSCs prepared by COSLL exhibit considerable areal capacitance of over 4 mF cm^-2, which is comparable to that of the polyimide-LIG-based counterpart. COSLL is also compatible with complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical system (MEMS) processes, enabling the fabrication of LIG/Au MSCs with comparable areal capacitance and lower internal resistance. Furthermore, the as-prepared MSCs demonstrate excellent mechanical robustness, long-cycle capability, and ease of series-parallel integration, benefiting their practical application in various scenarios. With the use of eco-friendly biomass carbon source and convenient process flowchart, the COSLL emerges as an attractive method for the fabrication of flexible LIG on-chip MSCs and various other advanced LIG devices.

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Driven by the increasing demand for high-power systems, ceramic substrates have received more attention for handling higher power density. Warpage in active metal brazed (AMB) ceramic substrate becomes a critical issue as it can deteriorate the reliability performance. This study comprises three phases, including investigation of the cause of the warpage, validation of the proposed model, and optimization for effective warpage management. At first, the coefficient of thermal expansion (CTE) and yield strength of the copper (Cu) layer in AMB were characterized and adopted in a two-dimensional (2D) finite element model. The evolution of simulated strain and moments revealed the cause of the warpage during the manufacturing processes. Furthermore, the 2D model was extended to a three-dimensional (3D) model. The finite element method (FEM) and experiments were conducted on different heat treatment conditions for 3D model validation. The validated 3D model was applied to carry out a design of experiments (DoEs) for design optimization to reduce the warpage. Consequently, the factor analysis in DoEs was demonstrated by different pattern designs using subtractive milling techniques.@en

Electromigration (EM) is a crucial failure mode in Aluminum (Al) interconnection wires those are widely used in high density semiconductor packaging. This study systematically investigated the influence of EM on the mechanical properties of Al interconnects via nanoindentation experiments and molecular dynamics (MD) simulations. The results are list as follows. (1) The indentation depth gradually increases with the increase in indentation load, resulting in a gradual increase and stabilization of the Young’s modulus and hardness of the structure. Within a specific range, the influence of the loading rate on the indentation depth and mechanical properties is relatively small. (2) The region where Young’s modulus of the interconnect decreases correlates with the location where EM-induced voids initiate. EM-induced voids have a direct impact on the material’s mechanical properties, particularly the decrease in Young’s modulus. (3) These EM-induced voids affect the nucleation and formation of dislocations. With the increase in void concentration and indentation depth, The generation and slip of dislocations increase as the void concentration and indentation depth increase, leading to a decrease in the material’s mechanical properties over time. This comprehensive findings expand the knowledge on mechanical behavior degradation of Al interconnects when EM failure occurs, providing a scientific basis for designing and optimizing high density semiconductor packaging.@en