This paper compares and evaluates the single pulse short-circuit robustness of SiC MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.@en

The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L JFET=1.4μ m has the best HF-FOM (R on × Cgd) and HF-FOM (R on × Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.@en

Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller Rb and more difficult to active parasitic BJT.@en

A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (C_gd) and gate-to-drain charge (Q_gd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [R_on × C_gd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [R_on × Q_gd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.

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A partial carrier stored and hole path floating dummy shield trench IGBT (PCS-FD-IGBT) is proposed and investigated by simulation. Under E_off of 8mJ/cm², the V_CE(sat)) of 1200V class PCS-FD-IGBT is 1.223V, which is 11.1% and 2.2% less than CON-FD-IGBT and HP-FD-IGBT. Besides, the EMI noise of PCS-FD-IGBT is suppressed at a lower level (dV/dt is below 80kV/μs). Moreover, the PCS-FD-IGBT improves the gate drive controllability to easily adapt the larger range of system inductance.

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Using TCAD simulations, the silicon carbide metal-oxide-semiconductor field-effect transistor with p-type floating islands (SiC FLIMOSFET) is systematically investigated in this paper. The doping concentration (N _FLI ), length (L), and position (D1) of floating islands are optimized according to breakdown voltage (BV), electric field distribution, and on-resistance. The results show that NFLI = 1 × 10 ¹⁷ cm ^-3 , L = 2.5 μm, and D1 = 9.0 μm are superior values for FLI structure considering tradeoff between BV and on-resistance. With the same BV capacity, the on-resistance of SiC FLIMOSFET is decrease by 32% comparing to the conventional SiC VDMOSFET. Besides, the dynamic property shows 16.5% reduction of FoM R _{on} cdot Q _GD in the SiC FLIMOSFET. Significantly, comparing to the conventional structure, the electro-thermal simulation indicates that the SiC FLIMOSFET has a higher robustness under short-circuit condition owing to the reduction of thermal stress in SiC/SiO ₂ interface. All the results show that the SiC FLIMOSFET has a good potential in SiC power device.

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The sensing properties of pristine, B-, Al-, Si-, and S-doped blue phosphorus (BP) monolayer to nitric oxide (NO) are theoretically investigated using density functional theory and non-equilibrium Green's function method. We systematically discuss the concentration effect, sensing mechanism, and current-voltage (I-V) response of BP adsorbing NO molecule. Our results show that the pristine BP exhibits a weak sensitivity for NO molecule, while B-, Al-, and Si-doped BP strongly adsorb NO via robust chemical bonds, meaning a good potential in metal-free catalysts, but unsuitable as NO sensors. Interestingly, S-doped BP is recommended as a desirable material for NO detection due to moderate adsorption energy and large charge transfer. Besides, the flowing current in S-doped BP can be significantly improved after NO adsorption under the same bias voltage. Therefore, S-doped BP could be a good candidate as an NO sensor.

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