Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

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A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

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Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

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This paper presents a Switching-Mode Regulating Rectifier (SM-RR) with single-stage dual-output regulation for biomedical wireless power transfer applications. To achieve both a high power conversion efficiency (PCE) and a long power transfer distance, the proposed SM-RR can seamlessly switch its operation between voltage mode and resonant current mode. To meet multi-power-rail requirements in loading circuits, it employs only three power transistors to provide two regulated outputs with parallel pulse-frequency modulation, which achieves unobservable cross-regulations. The prototype chip, fabricated in a 180 nm CMOS process, achieves two regulated outputs at 1.8 V and 3.3 V, respectively, up-to- 92.33% PCE, and up-to-42% transfer range extension compared to conventional voltage-mode receivers.

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In this paper, we present an equivalent circuit model that integrates a living myocardial slice (LMS) cultured on a microelectrode array (MEA) to effectively simulates a heart-on-a-chip (HoC) within Electronic Design Automation (EDA) software. The cardiac fiber model consists of cardiomyocytes interconnected by gap junctions to simulate the action potential (AP) conduction in the longitudinal direction. We systematically explored several parameters, including gap junction resistors, seal resistors, and electrode diameters, to assess their effects on local field potential (LFP). The model accuracy was validated through in vitro experiments using mouse LMS, confirming its potential for guiding HoC design in cardiac research.

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This article presents a 10mV-startup-voltage thermoelectric energy harvesting system, assisted by a piezoelectric generator (PEG) as a cold starter. It exploits the fact that when a thermoelectric energy harvesting system is implemented in a place where kinetic energy is also present, the PEG starter can provide a clock signal to start the system. Thanks to the high output impedance of the PEG, the generated clock voltage can easily go over several hundreds of mV, which can be used to drive the boost converter to harvest thermoelectric energy even at an extremely low thermoelectric generator (TEG) voltage. The proposed system was fabricated in a 180-nm BCD process. The measurement results show that the TEG system can start up from the cold state with a TEG voltage as low as 10 mV while maintaining a 63.9% efficiency. The peak power conversion efficiency reaches 83.7% when the TEG voltage is 55 mV.@en

Piezoelectric energy harvesting (PEH) has been considered a promising solution for replacing conventional batteries to power wireless sensors. A complete PEH system typically includes three stages: ac-dc rectification, maximum power point tracking (MPPT), and output voltage regulation to power the load circuits. Unfortunately, most prior works focus only on the first one or two stages. A few employ three, but unfortunately, they are in cascaded stages, which results in cascaded power efficiency loss. This article proposes a single-stage bias-flip MPPT regulating rectifier (BMRR), which integrates the active bias-flip rectification, MPPT, and output voltage regulation into one stage. The proposed BMRR transfers energy from the piezoelectric transducer (PT) directly to the output capacitor by employing fewer switches, removing the conventional bridge rectifier, and eliminating cascaded energy loss. In addition, the design was implemented in a fully digital fast-MPPT technique based on an improved duty-cycle-based (DCB) algorithm to let the PT voltage jump to the maximum power point (MPP) in only one step. The proposed BMRR rectifier was fabricated in a 180-nm BCD process. The measured results show 930% power enhancement compared to a full bridge rectifier (FBR) and 92.5% end-to-end (E2E) efficiency.

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When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.

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The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term monitoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing technique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286 Omega and 162 fF, respectively. The power consumption and die area are reduced to 0.74 mu text{W} /Channel and 0.038 mm2/Channel, respectively.

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Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.

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A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

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Piezoelectric energy harvesting (PEH) is a promising approach to collecting ambient kinetic energy as the power supply for electronic devices. In many PEH designs, the maximum power point tracking (MPPT) technique is exploited to enhance the output power of the system. However, a typical PEH system requires a separate power stage for MPPT, which requires a large external rectified capacitor for MPPT operation and suffers from cascaded power efficiency loss. This paper presents an MPPT-integrated bias-flip rectifier where the MPPT and AC-DC rectifier are merged into one stage, resulting in fewer off-chip capacitors, faster MPPT, and less cascaded energy loss. The proposed circuit was fabricated in a 0.18μm CMOS process, and the measurement results show a 7.7 × energy extraction enhancement.

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This work presents a switched capacitor power converter (SCPC) with instant transient response and minimized steady-state output ripple. The proposed SCPC employs a hybrid control strategy that amalgamates the strengths of hysteresis and continuous frequency modulation (CFM) controls, thus elevating transient performance while maintaining a small steady-state ripple. The system adopts a 10 -phase interleaved recursive switched capacitor (RSC) topology with adaptive capacitor sizing to achieve configurable voltage-conversion ratios (VCR) with heightened efficiency, power density, and load ability. Additionally, a novel adaptive switch-sizing technique is introduced to improve light-load efficiency. Fabricated in 180-nm BCD technology, the chip supports a wide-range load current of 0.7mA-120mA and converts a 0.8 -to-3.6V input to a 0.25 -to2.4 V output with a peak efficiency of 87.1%. The proposed converter simultaneously achieves a low voltage ripple of 12 mV and an over-/under-shoot voltage of less than 50 mV even under significant load transient steps (171X).

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In this letter, a 6.78-MHz single-stage regulating voltage-doubling rectifier is presented for biomedical wireless power transfer (WPT) applications. Derived from a full-wave voltage doubler, a theoretical voltage conversion ratio (VCR) of 2 can be achieved, which benefits the end-to-end voltage gain of a biomedical WPT system with varying link conditions. As a result, a wider WPT operational range and less coil-link loss can be achieved. To avoid efficiency loss due to cascading, the rectifier output is in-situ regulated in a sub-50-mV hysteresis window by pulse-skipping control. To ensure a high power conversion efficiency (PCE), adaptive delay-compensated active diodes are adopted with an offset locking technique. The input/output capacitors of the rectifier are fabricated on-chip, achieving a fully integrated design. The rectifier was fabricated in a 180-nm BCD process, occupying a silicon area of 0.3/2.7 mm2 without/with on-chip capacitors. The measurements show that the rectifier can realize a peak PCE at 90.6% when the output power is 79.8 mW. The PCE and VCR are achieved higher than 86.4% and 1.6, respectively, over a large loading range (from 1 to 40 mA). The rectifier can output a maximum power of 159.2 mW, satisfying most biomedical implants.

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Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) dc-dc converters, based on several basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multiple VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This article presents a new recursive dc-dc converter system, which can dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in the conventional designs can be reused in this new architecture for increasing the load-driving capacity, power density, and power efficiency. To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of \text{0.71}\,\text{mA} and achieves a peak power efficiency of 93.1% with 105.3\,\mu \text{A/mm} {2} chip power density from a 2-V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236×, and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4, and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.

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Dual-output regulating rectifier is highly desired in wireless power transfer (WPT) for sub-100mW bioimplants. Such rectifiers perform voltage rectification and dual-output regulation simultaneously, thus avoiding post DC-DC conversions and cascaded power losses [1 –4]. However, the conventional dual-output structure suffers from a low voltage conversion ratio (VCR) (< 1) due to the full bridge rectifier (FBR) topology (Fig. 1), severely limiting the receiver operation when wireless link condition varies [1–2]. In order to extend the operational range without increasing the power demand from the transmitter, [3] presents a charge-pump based dual-output rectifier; however, it uses 10 power transistors (PTs) and 8 off-chip capacitors, degrading the power conversion efficiency (PCE) and increasing the integration cost. Alternatively, the current-mode dual-output rectifier can realize a VCR higher than 1, but the output power is limited to less than 10mW [4], which is insufficient for advanced bioimplants. In this work, a 13. 56MHz single-stage dual-output voltage doubler (DOVD) is proposed to address the above limitations, which employs only two PTs and a fully integrated design. lt can achieve a peak VCR of1.78 and outputs power up to 8lmWwith a 91.8% peak PCE.@en

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V.@en

Synchronized bias-flip rectifiers, such as synchronized switch harvesting on inductor (SSHI) rectifiers, are widely used for piezoelectric energy harvesting (PEH) [1], which can replace the use of batteries in many loT applications, thus reducing both system volume and maintenance cost. However, the output power extracted by such rectifiers strongly depends on the impedance matching between the piezoelectric transducer (PT) and the circuit. To maximize this, two maximum power point tracking (MPPT) algorithms are often used. As shown in Fig. 30.3.1 (left), the Perturb & Observe (P&O) (a.k.a. hill-climbing) algorithm adjusts the rectified output power in a stepwise manner towards the maximum power point (MPP), thus establishing robust and continuous MPPT. However, accurately sensing the rectified output power often requires complex and power-hungry hardware [1], [2]. Another simpler algorithm is based on the fractional open-circuit voltage (FOCV) and involves periodically measuring the PT's open-circuit voltage amplitude (VOC) and regulating the rectified voltage (VREC) to a level (VMPP), which corresponds to the MPP [3-6]. However, the PT must be periodically disconnected from the rectifier to measure VOC, resulting in wasted energy, while the inherent delay in sensing VOC variations reduces the overall tracking efficiency. Furthermore, a calibration step is usually necessary to determine VMPP, since this depends on the actual PT voltage flip efficiency (etaF) of the bias-flip rectifier.

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This article presents a piezoelectric energy harvesting (PEH) interface circuit using a new self-bias-flip with the charge recycle (SBFR) technique without employing any additional energy reservoir. Traditional designs, including synchronous-switch harvesting on inductor (SSHI), synchronous-switch harvesting on capacitor (SSHC), synchronous electric charge extraction (SECE), etc., require additional capacitors or inductors to reverse the voltage on the PEH at the zero-crossing point. This design innovatively uses the inherent capacitors of the piezoelectric harvesters as the flipping capacitors. In order to improve the extract efficiency of the interface, the zero-crossing state is split into a charge recycle stage and a voltage-flip stage. For a piezoelectric array with 2^n PEHs, a configuration with (n-1) phases in the charge recycle stage is adopted to reduce the loss caused by direct charge neutralization. The charge redistribution loss is reduced by employing (2n+1) phases in the voltage-flip stage. The proposed principle has been implemented with discrete components and is verified by three different prototypes. The measurement results show that a flipping efficiency of 67% is achieved by utilizing SBFR with four PEHs. And the proposed interface can provide up to 5.2x improvement when compared with the full-bridge rectifier (FBR).

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A triboelectric nanogenerator (TENG) is a new transducer utilizing contact electrification and electrostatic induction to transform mechanical energy into electric energy. Due to its high energy density and flexibility, it can be employed to make electronic devices self-powered by harvesting ambient mechanical energy in many application scenarios, such as biomedical devices, wearable electronics, and Internet-of-Things (IoT) sensors. However, due to the time-varying and low internal capacitance of a TENG, it is challenging to extract electrical energy from it. Hence, good power conversion techniques are crucial in TENG energy harvesting systems. Currently, studies on dedicated integrated power conversion techniques are very limited. Due to the exponentially increasing research interests in TENG, a comprehensive study on the TENG energy harvesting system, emphasizing integrated-circuit (IC) power conversion techniques, is urgently needed. This paper summarizes and compares the state-of-the-art triboelectric energy harvesting systems, focusing on different power conversion techniques for output power enhancement. Some techniques, which have been widely used in other relevant energy harvesting systems, are also mentioned to inspire innovative design strategies for TENG systems.

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