Various bias-flip rectifiers were proposed to improve the energy extraction performance for piezoelectric energy harvesting (PEH), which requires a power supply. However, no stable power supply is available when the system starts from a cold state. Typically, during the cold state, the system operates as a passive full bridge rectifier (FBR) to build up a stable power supply by charging a capacitor and then switching to the active rectifier after the cold state. Unfortunately, the system cannot start up if the open circuit voltage from a piezoelectric transducer (PT) is lower than the required supply voltage level. As a result, the system would end up with cold startup failure. This paper proposes a 2-mode bias-flip rectifier, which addresses the startup issue by lowering the required input open circuit voltage from the PT. The proposed design was fabricated in a 180-nm BCD process. Measurement results show that the necessary open-circuit voltage from the PT is lowered by 73% to achieve a successful cold startup, and the proposed system achieves 1182% energy extraction enhancement compared to a passive FBR.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

The various application scenarios of triboelectric nanogenerator (TENG) have attracted increasing research interest, while one of the biggest challenges is the energy extraction efficiency. Due to the small and time-varying inherent capacitor in a TENG, the previous energy extraction techniques e.g., full-bridge rectifier (FBR) and bias-flip (BF) rectifier, performed not well. To extract more energy from TENG, this article proposed a fully integrated switched-capacitor (SC) rectifier with an electrostatic charge boosting (ECB) technique, achieving simultaneous extraction from the synchronized triboelectric energy and self-excited electrostatic energy. The proposed rectifier was fabricated in a 180-nm BCD process. With the proposed ECB technique, the theoretical analysis and measurements show a quadratically increasing output power with respect to the rectification voltage, attaining a constant maximum power point (MPP) at the breakdown voltage of the circuit. A maximum output power of 127.6 μ W is measured with a TENG fabricated in-house. Compared to a passive FBR, the proposed rectifier enhances the output power by 14 times.

Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

In this paper, we present an equivalent circuit model that integrates a living myocardial slice (LMS) cultured on a microelectrode array (MEA) to effectively simulates a heart-on-a-chip (HoC) within Electronic Design Automation (EDA) software. The cardiac fiber model consists of cardiomyocytes interconnected by gap junctions to simulate the action potential (AP) conduction in the longitudinal direction. We systematically explored several parameters, including gap junction resistors, seal resistors, and electrode diameters, to assess their effects on local field potential (LFP). The model accuracy was validated through in vitro experiments using mouse LMS, confirming its potential for guiding HoC design in cardiac research.

When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.

This article proposes a novel collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs) rectifier and multioutput synchronous dc-dc converters with shared capacitors. Compared to the traditional SSHC, our CF-SSHC rectifier can increase the number of flipping phases, potentially enhancing the flipping efficiency and output power under specific conditions where C FLY is close to C_P. The synchronous dc-dc converters reuse the flying capacitors to achieve a high maximum output power improving rate (MOPIR) over a limited input power range and provide multiple outputs. This work achieves an advanced number of flipping phases in capacitor-based rectifier interface technology and explores multiple-input multiple-output configurations, evaluating the system's performance under periodic and shock conditions for the first time. The system's adaptability to various piezoelectric transducer (PT) array configurations is validated, highlighting its potential for Internet of Things (IoT) networks. The design is fabricated in standard 0.18- μ m CMOS. Measurement results demonstrate that the voltage flipping efficiency of up to 83% is achieved. Compared with full-bridge rectifier (FBR), the MOPIR can be increased to 5.06 × and 4.78 × under off-resonance and on-resonance excitation, respectively. It can also achieve a 2.14 × power enhancement under shock excitation. Additionally, when the input power P INFBR is in the range of 1.42-28.4 μ W, the MOPIR of the proposed system is always greater than 4.

Piezoelectric energy harvesting (PEH) has been considered a promising solution for replacing conventional batteries to power wireless sensors. A complete PEH system typically includes three stages: ac-dc rectification, maximum power point tracking (MPPT), and output voltage regulation to power the load circuits. Unfortunately, most prior works focus only on the first one or two stages. A few employ three, but unfortunately, they are in cascaded stages, which results in cascaded power efficiency loss. This article proposes a single-stage bias-flip MPPT regulating rectifier (BMRR), which integrates the active bias-flip rectification, MPPT, and output voltage regulation into one stage. The proposed BMRR transfers energy from the piezoelectric transducer (PT) directly to the output capacitor by employing fewer switches, removing the conventional bridge rectifier, and eliminating cascaded energy loss. In addition, the design was implemented in a fully digital fast-MPPT technique based on an improved duty-cycle-based (DCB) algorithm to let the PT voltage jump to the maximum power point (MPP) in only one step. The proposed BMRR rectifier was fabricated in a 180-nm BCD process. The measured results show 930% power enhancement compared to a full bridge rectifier (FBR) and 92.5% end-to-end (E2E) efficiency.

The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term monitoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing technique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286 Omega and 162 fF, respectively. The power consumption and die area are reduced to 0.74 mu text{W} /Channel and 0.038 mm2/Channel, respectively.

Piezoelectric energy harvesting (PEH) is a promising approach to collecting ambient kinetic energy as the power supply for electronic devices. In many PEH designs, the maximum power point tracking (MPPT) technique is exploited to enhance the output power of the system. However, a typical PEH system requires a separate power stage for MPPT, which requires a large external rectified capacitor for MPPT operation and suffers from cascaded power efficiency loss. This paper presents an MPPT-integrated bias-flip rectifier where the MPPT and AC-DC rectifier are merged into one stage, resulting in fewer off-chip capacitors, faster MPPT, and less cascaded energy loss. The proposed circuit was fabricated in a 0.18μm CMOS process, and the measurement results show a 7.7 × energy extraction enhancement.

Body Channel Communication (BCC) utilizes the body surface as a low-loss signal transmission medium, reducing the power consumption of wireless wearable devices. However, the effective communication range on the human body is limited in the state-of-the-art BCC transceivers, where the signal loss between the body surface and the BCC receiver remains one of the main bottlenecks. To reduce the interface loss, a high input impedance is desired by the BCC receiver, but the DC-biasing circuits decrease the input impedance. In this work, a dynamically-sampling IFE is proposed to eliminate the DC voltage bias, resulting in a 90kΩ; high input impedance and a 94dB RF—IF conversion gain to reduce the interface loss in long-range BCC applications. The BCC transceiver chip is fabricated in 55nm CMOS process, taking a die area of 0.123mm². Measured results show that the chip extends the BCC range to 2m for both the forward and backward paths, where the transmitter and receiver consume 711μW power in total.

This article presents a 13.56-MHz wireless power transfer (WPT) system with coupling variation robustness and high efficiency for powering biomedical implantable devices (IMDs). To sustain reliable power transfer against inductive-link fluctuation, a hybrid voltage-/current-mode (V/CM) receiver (RX) is proposed to provide CM recovery when the coupling becomes weak for VM operation. To optimize the end-to-end (E2E) efficiency, a digital pulsewidth modulation (PWM)-based global power regulation technique is proposed, which allows a fully on/off operation of the three-mode power amplifier (PA) at the transmitter (TX) side and fast load-transient responses. Moreover, the system adopts a fully integrated voltage-sensing load-shift-keying (LSK) demodulation technique, which replaces conventional current sensing methods with a streamlined implementation and reduced power consumption. Both prototype TX and RX chips were fabricated in a 180-nm CMOS process. The proposed system, powered by a 1.8-V supply at TX, realizes a regulated 1.8-V dc output at RX. With the help of the hybrid V/CM RX, the proposed system achieves an up-to-150% WPT range extension compared to VM-only operation and an up to 7.2-cm WPT range. Benefiting from the global digital-PWM regulation, it achieves up to 72.3% E2E efficiency over the loading range from 0.18 to 81 mW. A 10- μ s load-transient recovery is also attained at a 164 × load step with a 110-mV undershoot and unnoticeable overshoots.

This paper presents a Switching-Mode Regulating Rectifier (SM-RR) with single-stage dual-output regulation for biomedical wireless power transfer applications. To achieve both a high power conversion efficiency (PCE) and a long power transfer distance, the proposed SM-RR can seamlessly switch its operation between voltage mode and resonant current mode. To meet multi-power-rail requirements in loading circuits, it employs only three power transistors to provide two regulated outputs with parallel pulse-frequency modulation, which achieves unobservable cross-regulations. The prototype chip, fabricated in a 180 nm CMOS process, achieves two regulated outputs at 1.8 V and 3.3 V, respectively, up-to- 92.33% PCE, and up-to-42% transfer range extension compared to conventional voltage-mode receivers.

Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

This work presents a switched capacitor power converter (SCPC) with instant transient response and minimized steady-state output ripple. The proposed SCPC employs a hybrid control strategy that amalgamates the strengths of hysteresis and continuous frequency modulation (CFM) controls, thus elevating transient performance while maintaining a small steady-state ripple. The system adopts a 10 -phase interleaved recursive switched capacitor (RSC) topology with adaptive capacitor sizing to achieve configurable voltage-conversion ratios (VCR) with heightened efficiency, power density, and load ability. Additionally, a novel adaptive switch-sizing technique is introduced to improve light-load efficiency. Fabricated in 180-nm BCD technology, the chip supports a wide-range load current of 0.7mA-120mA and converts a 0.8 -to-3.6V input to a 0.25 -to2.4 V output with a peak efficiency of 87.1%. The proposed converter simultaneously achieves a low voltage ripple of 12 mV and an over-/under-shoot voltage of less than 50 mV even under significant load transient steps (171X).

In this article, we propose a reconfigurable regulating rectifier with a wide operational range for wireless power transfer. The proposed three-mode rectifier achieves a broad range voltage regulation without global loop control to minimize the chip area occupation. Compared with previous work, more working modes and greater voltage gain allow the proposed rectifier to regulate lower input power, which extends the voltage regulation range. A local loop control scheme is proposed for voltage rectification with three modes. It adaptively senses the duty cycle of the mode signal to determine the working mode of the rectifier, and configure the rectifier to the desired mode for voltage regulation. The proposed system was designed and fabricated in a 180-nm BCD technology with an active area of 1.17 mm2. The measurement results show that the proposed system can rectify wide-range input ac power to a regulated output. The achieved voltage conversion ratiois between 0.95X and 2.68X, with a peak power conversion efficiencyat 87.4%.