The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the 2nd-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show -92 dBc/Hz@10 kHz phase noise and 6.8 μ W power.

Synchronized switch harvesting on inductor (SSHI) rectifier has been verified as an efficient active rectifier to harvest kinetic energy in piezoelectric energy harvesting (PEH) system. Compared with passive rectifiers, active rectifiers including SSHI rectifier require a stable power supply to drive switches. However, when the system starts from the cold state, the required power supply is not available at first. For the active rectifiers, the active circuits work as a typical full bridge rectifier (FBR) until the stable power supply is built up. Unfortunately, a FBR cannot build up a stable power supply when the input open circuit voltage VOC is lower than the required power supply, resulting in disabled active rectifiers. This paper proposes a 2-mode reconfigurable SSHI rectifier design for low input VOC. By this method, the requirement for the input VOC is 3.2X lower than a FBR. The proposed system is designed in a 0.18µm process and post-layout simulations verify the cold start-up process under low VOC voltage.

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

A nanopower highly efficient low-dropout (LDO) regulator for energy harvesting (EH) applications is presented in this paper. The LDO is fully autonomous with a bandgap reference (BGR) featuring a novel bandgap supply-switching (SS) topology, an over-voltage protection (OVP), a under-voltage lockout (UVLO) and control block to obtain stable output and robust cold-start. The system provides configurable voltage supply (1.1 \sim2V) for potential loads, while consuming as low as 66 nW power. The entire system achieves a peak power efficiency of 95.6% at Vout=2V and I-{\iota-{oad}}=100\muA.

Harvesting energy from environments has been a promising approach to power ubiquitously distributed Internet of Things (IoT) devices. For harvesting kinetic energy with piezoelectric transducers, synchronized switch harvesting on capacitors (SSHC) rectifiers have been demonstrated to achieve high energy extraction performance without using any inductor. In previous studies, the switched capacitors in SSHC rectifiers are chosen equal to the inherent capacitance of the piezoelectric transducer (PT) to achieve good voltage flip efficiencies at 33.3%, 50% and 66.7% for 1-, 2- and 4-stage SSHC rectifiers, respectively. However, with much larger switched capacitors and the same SMD package size, this paper finds that the voltage flip efficiency can be further increased to 50%, 66.7% and 80% for 1-, 2- and 4-stage SSHC rectifiers, respectively; as a result, the output power can be greatly increased. This paper also finds that the proposed design only requires half number of capacitors to achieve the same voltage flip efficiency for conventional SSHC rectifiers, which significantly reduces the system form factor for miniaturization.