High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.@en

This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm² and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.

@en