Objective. Bi-directional electronic neural interfaces, capable of both electrical recording and stimulation, communicate with the nervous system to permit precise calibration of electrical inputs by capturing the evoked neural responses. However, one significant challenge is that stimulation artifacts often mask the actual neural signals. To address this issue, we introduce a novel approach that employs dynamical control systems to detect and decipher electrically evoked neural activity despite the presence of electrical artifacts. Approach. Our proposed method leverages the unique spatiotemporal patterns of neural activity and electrical artifacts to distinguish and identify individual neural spikes. We designed distinctive dynamical models for both the stimulation artifact and each neuron observed during spontaneous neural activity. We can estimate which neurons were active by analyzing the recorded voltage responses across multiple electrodes post-stimulation. This technique also allows us to exclude signals from electrodes heavily affected by stimulation artifacts, such as the stimulating electrode itself, yet still accurately differentiate between evoked spikes and electrical artifacts. Main results. We applied our method to high-density multi-electrode recordings from the primate retina in an ex vivo setup, using a grid of 512 electrodes. Through repeated electrical stimulations at varying amplitudes, we were able to construct activation curves for each neuron. The curves obtained with our method closely resembled those derived from manual spike sorting. Additionally, the stimulation thresholds we estimated strongly agreed with those determined through manual analysis, demonstrating high reliability ( R 2 = 0.951 for human 1 and R 2 = 0.944 for human 2). Significance. Our method can effectively separate evoked neural spikes from stimulation artifacts by exploiting the distinct spatiotemporal propagation patterns captured by a dense, large-scale multi-electrode array. This technique holds promise for future applications in real-time closed-loop stimulation systems and for managing multi-channel stimulation strategies.

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Climate and justice are interconnected. However, simply raising ethical issues associated with the links between climate change, technology, and health is insufficient. Rather, policies and practices need to consider ethics ahead of time. If it is only added “after the fact,” policy will be less efficient and opportunities for carbon minimization will be lost. This will require the cooperation of people at many levels and can be guided by two essential ethical principles: distributive justice and environmental sustainability.@en

This brief presents a low-power oscillatory synchronization feature extraction (FE) unit for phase-amplitude coupling (PAC) and phase locking value (PLV) features. The proposed FE unit uses a new multiplier-less wavelet approximation in combination with a multi-rate lowpass filter bank for low-power complex signal extraction. Further power and area reductions are obtained by utilizing a light sine and cosine extractor (LSCE) for the feature computation. The synthesized 32-channel design achieves state-of-the-art performances in post-layout simulations at 430 nW/channel and 0.36 mm2 while maintaining sufficient accuracy for seizure detection in epileptic patients.

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Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.

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This article presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain–computer interfaces (BCIs). The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse-position modulation (PPM)-based active digital pixels (ADPs) with a global single-slope (SS) analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 µm that can be directly matched to a high-density micro-electrode array (MEA). The pixel achieves 7.4-µV_rms input-referred noise with a −3-dB bandwidth of 300 Hz–5 kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 µm²) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

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Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this article, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50× compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell-type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000× compression can be achieved over the baseline recordings.

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This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 μ m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 μ VRMS input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.

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This paper introduces a fast artifact recovery algorithm (FARA) that uses electrochemical impedance spectroscopy to model the electrode-tissue interface and design an optimum stimulation waveform to minimize the residual artifact duration in single-cell resolution neural interfaces. Results in saline solution with a custom PCB and a 30 $\mu \mathrm{m}$ diameter microelectrode array show a worst case artifact recovery time of 160 $\mu \mathrm{s}$ when measured from the end of the working phase (anodic 500 $\mathrm{n}\mathrm{A}, 250\mu \mathrm{s})$. On average, the proposed algorithm provides an 81% improvement over a triphasic charge-balanced stimulation waveform.@en

This paper investigates the efficacy of a wired-OR compressive readout architecture for neural recording, which enables simultaneous data compression of action potential signals for high channel count electrode arrays. We consider a range of wiring configurations to assess the trade-offs between compression ratio and various task-specific signal fidelity metrics. We consider the fidelity in threshold crossing detection, spike assignment, and waveform estimation, and find that for an event SNR of 7-10 the readout captures at least 80% of the spike waveforms at ∼150x data compression.@en

This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit's unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately 2× and 10×, respectively. The 1.44 mm 2 chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature.@en

Modeling linear periodically time-varying (LPTV) circuits is challenging due to the presence of frequency translation. Many approaches have been proposed that simplify the analysis and provide intuition into the operation of these circuits. It is critical to select the proper model when designing LPTV systems: too complex, and intuition is lost; too simple, and numerical accuracy degrades. This work shows how a conversion matrix-based model can be used for mixer-first receivers with complex feedback in the presence of finite switch transitions. This model accurately predicts S11 below -10 dB for all tested transition times, in contrast with prior models, which are shown to be invalid with transitions beyond 2% of the clock period. As a design tool, this approach models gain, harmonic rejection ratio, and noise figure within 0.1 dB of simulation with switch transitions even at 5% of the clock period.

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The efficacy of wireless intracortical brain–computer interfaces (iBCIs) is limited in part by the number of recording channels, which is constrained by the power budget of the implantable system. Designing wireless iBCIs that provide the high-quality recordings of today’s wired neural interfaces may lead to inadvertent over-design at the expense of power consumption and scalability. Here, we report analyses of neural signals collected from experimental iBCI measurements in rhesus macaques and from a clinical-trial participant with implanted 96-channel Utah multielectrode arrays to understand the trade-offs between signal quality and decoder performance. Moreover, we propose an efficient hardware design for clinically viable iBCIs, and suggest that the circuit design parameters of current recording iBCIs can be relaxed considerably without loss of performance. The proposed design may allow for an order-of-magnitude power savings and lead to clinically viable iBCIs with a higher channel count.

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Brain-machine interfacesBrain-machine interface (BMIs) of the future will be used to treat diverse neurological disorders and augment human capabilities. However, to realize this futuristic promise will require a major leap forward in how electronic devices interact with the nervous system. Current BMIs provide coarse communicationCommunication with the target neural circuitry, because they fail to respect its cellular and cell-type specificity. Instead, they indiscriminately activate or record many cells at the same time and provide only partial restoration of lost abilities. A future BMI that may pave the path forward is an artificialRetina retinaArtificial retina---a device that can restore vision to people blinded by retinal degeneration. Because the retina is relatively well understood and easily accessible, it is an ideal neural circuit in which to develop a BMI that can approach or exceed the performance of the biological circuitry. This chapter summarizes the basic neuroscienceNeuroscience of vision, identifies the requirements for an effective retinal interface, and describes some of the necessary circuits and systems. Based on these ideas and the lessons from first-generation retinal prosthesesBionic, a novel neuroengineering approach is proposed: the first BMI that will interact with neural circuitry at cellular and cell-type resolution.@en

Current retinal prostheses provide electrical stimulation without feedback from the stimulated neurons. Incorporation of multichannel recording electronics would typically require trans-scleral cables for power supply and data transmission. In this work, we explore a wireless, optoelectronic, miniature, modular, and distributed electro-neural interface for recording, which we call Sensory Particles with Optical Telemetry (SPOT). It can be used in an advanced, bi-directional retinal prosthesis and other sensory applications. Emphasis is placed on the novel telemetry stage. SPOTs are powered by near-infrared light and transmit information by light. As a proof of concept, we designed and built a low-power, small-footprint linear transconductance circuit utilizing chopper stabilization in 130nm CMOS. Our design achieved 57 mS transconductance within 3.5 kHz bandwidth, and a near-infrared (NIR) power density of 0.5 mW/mm², well within the ocular and thermal safety limits. The telemetry circuit consumes 0.015 mm² area, and each SPOT can be powered by a single photovoltaic (PV) supply of area 0.0056 mm². Electrical spikes transmitted by an 850nm LED were detected with 15 dB SNR, at the output of the optical link.

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Neural interfaces of the future will be used to help restore lost sensory, motor, and other capabilities. However, realizing this futuristic promise requires a major leap forward in how electronic devices interface with the nervous system. Next generation neural interfaces must support parallel recording from tens of thousands of electrodes within the form factor and power budget of a fully implanted device, posing a number of significant engineering challenges. In this paper, we exploit sparsity and diversity of neural signals to achieve simultaneous data compression and channel multiplexing for neural recordings. The architecture uses wired-OR interactions within an array of single-slope A/D converters to obtain massively parallel digitization of neural action potentials. The achieved compression is lossy but effective at retaining the critical samples belonging to action potentials, enabling efficient spike sorting and cell type identification. Simulation results of the architecture using data obtained from primate retina ex-vivo with a 512-channel electrode array show average compression rates up to  ∼ 40× while missing less than 5% of cells. In principle, the techniques presented here could be used to design interfaces to other parts of the nervous system.

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Always-on sound classification is a desirable but power-intensive function for a variety of emerging Internet of Everything applications. This work explores the accuracy-complexity tradeoff by using summary statistics for classifying semi-stationary sounds. Compared to contemporary solutions including deep learning, this approach requires one to three orders of magnitude fewer parameters and can therefore be trained over ten times faster. We propose a mixed-signal design using N-path filters for feature extraction to further improve energy efficiency without incurring a large accuracy penalty for a binary classification task (less than 2.5% area reduction under receiver operating characteristic curve).

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This paper describes an architecture for the massively parallel digitization of neural action potentials. The scheme achieves simultaneous data compression and channel multiplexing through wired-OR interactions within an array of single-slope A/D converters. The achieved compression is lossy but effective at retaining the critical samples belonging to action potential spikes. Simulation results using ex-vivo experimental data from a 512-channel array show compression rates up to ∼73x while maintaining ≥90% reconstruction coverage for parasol cells in the primate retina.

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This letter presents a low-noise integrated potentiostat for affinity-free molecular detection in applications for personalized medicine. The affinity-free sensing technique uses a digital classifier to identify molecules through unique vibrational signatures. The sensing mechanism relies on coherent interference of electron wave functions at the interface between a nanoscale working electrode and a liquid electrolyte. Coherence at the sensing interface is enabled by low-noise feedback, which reduces the effective temperature of the electrons. The described three-channel potentiostat IC uses chopping and correlated double sampling to achieve an input-referred voltage noise of 12 nV/rt-Hz at 30 Hz and a current resolution of 1.8 pA_rms with 0.5-s averaging time. Each channel consumes 5 mW and occupies 0.41 mm² in 65-nm CMOS.

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This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

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