Modeling linear periodically time-varying (LPTV) circuits is challenging due to the presence of frequency translation. Many approaches have been proposed that simplify the analysis and provide intuition into the operation of these circuits. It is critical to select the proper model when designing LPTV systems: too complex, and intuition is lost; too simple, and numerical accuracy degrades. This work shows how a conversion matrix-based model can be used for mixer-first receivers with complex feedback in the presence of finite switch transitions. This model accurately predicts S11 below -10 dB for all tested transition times, in contrast with prior models, which are shown to be invalid with transitions beyond 2% of the clock period. As a design tool, this approach models gain, harmonic rejection ratio, and noise figure within 0.1 dB of simulation with switch transitions even at 5% of the clock period.

The efficacy of wireless intracortical brain–computer interfaces (iBCIs) is limited in part by the number of recording channels, which is constrained by the power budget of the implantable system. Designing wireless iBCIs that provide the high-quality recordings of today’s wired neural interfaces may lead to inadvertent over-design at the expense of power consumption and scalability. Here, we report analyses of neural signals collected from experimental iBCI measurements in rhesus macaques and from a clinical-trial participant with implanted 96-channel Utah multielectrode arrays to understand the trade-offs between signal quality and decoder performance. Moreover, we propose an efficient hardware design for clinically viable iBCIs, and suggest that the circuit design parameters of current recording iBCIs can be relaxed considerably without loss of performance. The proposed design may allow for an order-of-magnitude power savings and lead to clinically viable iBCIs with a higher channel count.

Current retinal prostheses provide electrical stimulation without feedback from the stimulated neurons. Incorporation of multichannel recording electronics would typically require trans-scleral cables for power supply and data transmission. In this work, we explore a wireless, optoelectronic, miniature, modular, and distributed electro-neural interface for recording, which we call Sensory Particles with Optical Telemetry (SPOT). It can be used in an advanced, bi-directional retinal prosthesis and other sensory applications. Emphasis is placed on the novel telemetry stage. SPOTs are powered by near-infrared light and transmit information by light. As a proof of concept, we designed and built a low-power, small-footprint linear transconductance circuit utilizing chopper stabilization in 130nm CMOS. Our design achieved 57 mS transconductance within 3.5 kHz bandwidth, and a near-infrared (NIR) power density of 0.5 mW/mm², well within the ocular and thermal safety limits. The telemetry circuit consumes 0.015 mm² area, and each SPOT can be powered by a single photovoltaic (PV) supply of area 0.0056 mm². Electrical spikes transmitted by an 850nm LED were detected with 15 dB SNR, at the output of the optical link.

Always-on sound classification is a desirable but power-intensive function for a variety of emerging Internet of Everything applications. This work explores the accuracy-complexity tradeoff by using summary statistics for classifying semi-stationary sounds. Compared to contemporary solutions including deep learning, this approach requires one to three orders of magnitude fewer parameters and can therefore be trained over ten times faster. We propose a mixed-signal design using N-path filters for feature extraction to further improve energy efficiency without incurring a large accuracy penalty for a binary classification task (less than 2.5% area reduction under receiver operating characteristic curve).

This letter presents a low-noise integrated potentiostat for affinity-free molecular detection in applications for personalized medicine. The affinity-free sensing technique uses a digital classifier to identify molecules through unique vibrational signatures. The sensing mechanism relies on coherent interference of electron wave functions at the interface between a nanoscale working electrode and a liquid electrolyte. Coherence at the sensing interface is enabled by low-noise feedback, which reduces the effective temperature of the electrons. The described three-channel potentiostat IC uses chopping and correlated double sampling to achieve an input-referred voltage noise of 12 nV/rt-Hz at 30 Hz and a current resolution of 1.8 pA_rms with 0.5-s averaging time. Each channel consumes 5 mW and occupies 0.41 mm² in 65-nm CMOS.

This paper describes an architecture for the massively parallel digitization of neural action potentials. The scheme achieves simultaneous data compression and channel multiplexing through wired-OR interactions within an array of single-slope A/D converters. The achieved compression is lossy but effective at retaining the critical samples belonging to action potential spikes. Simulation results using ex-vivo experimental data from a 512-channel array show compression rates up to ∼73x while maintaining ≥90% reconstruction coverage for parasol cells in the primate retina.

Neural interfaces of the future will be used to help restore lost sensory, motor, and other capabilities. However, realizing this futuristic promise requires a major leap forward in how electronic devices interface with the nervous system. Next generation neural interfaces must support parallel recording from tens of thousands of electrodes within the form factor and power budget of a fully implanted device, posing a number of significant engineering challenges. In this paper, we exploit sparsity and diversity of neural signals to achieve simultaneous data compression and channel multiplexing for neural recordings. The architecture uses wired-OR interactions within an array of single-slope A/D converters to obtain massively parallel digitization of neural action potentials. The achieved compression is lossy but effective at retaining the critical samples belonging to action potentials, enabling efficient spike sorting and cell type identification. Simulation results of the architecture using data obtained from primate retina ex-vivo with a 512-channel electrode array show average compression rates up to  ∼ 40× while missing less than 5% of cells. In principle, the techniques presented here could be used to design interfaces to other parts of the nervous system.

This paper presents a novel architecture for capacitive sensor interfaces that is insensitive to electro magnetic interferers in hostile environments. A bridge structure, with a feedback control and a special band-pass filter, overcomes the problems that affect the standard approaches. Behavioural level simulations demonstrate the feasibility of the idea for 12-bit resolution.

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm² and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

Ultra high-speed comparators for data-converters operating with conversion rate of 10+ GS/s are discussed. It is shown that the use of nanometer technologies and specific architectures allow comparator speeds in the 30 ps range or below. State-of-the-art schemes of latch are critically analysed and strategies for enhancing the speed are discussed. A novel scheme, the latch with embedded preamp, increases the speed of the fast scheme by almost a factor 2.