A 1024-Channel 268-nW/Pixel 36 × 36 µm²/ Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces

Abstract

This article presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain–computer interfaces (BCIs). The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse-position modulation (PPM)-based active digital pixels (ADPs) with a global single-slope (SS) analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 µm that can be directly matched to a high-density micro-electrode array (MEA). The pixel achieves 7.4-µV_rms input-referred noise with a −3-dB bandwidth of 300 Hz–5 kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 µm²) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.