The exponential growth in the scale and complexity of neural recording systems demands increasingly efficient computational frameworks to manage the vast data generated by modern multi-electrode ar- rays. This thesis explores the feasibility of integrating Graphics Processing Unit (GPU) acceleration with the Open Ephys ONIX system to enhance its support for next-generation neural interfaces and compu- tational algorithms. ONIX, a modular and open-source electrophysiology platform, currently relies on CPU-based computations that may struggle to meet the rising demands of closed-loop experiments. This work investigates PCIe peer-to-peer (P2P) communication between ONIX and GPUs to by- pass CPU involvement, aiming to reduce latency and increase throughput. A secondary data channel was implemented on the ONIX FPGA, accompanied by a custom kernel driver integrating GPUDirect with the existing RIFFA driver. Performance evaluations compared unpinned and pinned GPUDirect transfers to traditional CPU-mediated methods. Pinned transfers reduced transfer times by up to 30% for small data and 14% for larger data sizes, though significant variance in transfer time was observed. Application-level benchmarks revealed that GPU acceleration provides advantages for larger data sizes and higher computational loads but the effectiveness of GPUDirect is limited by ONIX’s PCIe through- put. The findings highlight that while GPUDirect offers theoretical benefits, its practical impact is con- strained by hardware limitations, including the PCIe bandwidth of the ONIX FPGA. This thesis out- lines necessary hardware improvements, such as higher-speed SerDes modules and advanced FPGA cards, to fully realize the potential of GPU acceleration in electrophysiology systems. A decision tree framework is proposed to guide researchers in determining scenarios where GPU and GPUDirect in- tegration is beneficial. While this study demonstrates the feasibility of GPU integration with ONIX, GPUDirect integration is currently not a beneficial technology for the ONIX ecosystem.

This thesis describes the design and simulation of a capacitively-coupled autozeroed and chopped operational amplifier in the TSMC high-voltage BCD 0.18 μm 5 V technology. It uses chopping and autozeroing to achieve high precision (10 μV offset and 50 nV/√Hz noise density) and a capacitively-coupled input stage to safely handle beyond-the-rails 50 V input voltages. The amplifier employs a pseudo-continuous time architecture that periodically autozeroes a single signal path, which is also chopped. Compared to amplifiers with ripple-reduction loops, this approach should potentially result in area and power savings. However, it also means that the signal path is periodically broken during a short deadtime, during which the signal path is autozeroed. Since the presence of the deadtime comes with a noise penalty, the amplifier’s clocking scheme has been optimized to reduce the length of the deadtime relative to the length of the two amplification phases. The simulated performance of the resulting amplifier is comparable with that of other precision amplifiers, while its chip area should be lower, resulting in lower production costs.

Purkinje cell is a type of neuron that can be found in the cerebellum. What characterises Purkinje cell neural activity is the fact that it exhibits two types of spiking behaviour; the so-called simple and complex spikes. These two types of spikes are thought to play a role in motor functionality. In order to better understand the relationship between Purkinje cell neural activity and the motor-cortex, neuroscientists record such neural activity in mice. However, current experimental setups pose a challenge as they involve a wired connection between the animal’s head stage and the recording device, which limits the mouse’s natural behaviour by restricting its movement. This work proposes a lightweight neural-spike detection and classification architecture for acquiring Purkinje cell neural activity. The proposed design discards unneeded information, by detecting and classifying spikes in real-time. This type of compression enables data storage on a removable device in the head stage, freeing mice from wires. Its small formfactor allows unrestricted movement during experiments, while a power-efficient design ensures long-termoperation. The performance of the algorithm has been evaluated using a software implementation, yielding a combined accuracy for detection and classification ranging from 92.74% to 94.54%. The system has been synthesised using the 45 nm Nangate Open Cell library resulting in an ASIC with an area of 0.22mm2 and a power consumption of 0.412mW.

This thesis presents the design of a low-power, sub-1V, BJT-based temperature sensor. It is based on a capacitively-biased (CB) BJT front-end, in which capacitors are discharged across diode-connected BJTs to obtain proportional-to-temperature (PTAT) and complementary-to-temperature (CTAT) voltages. These voltages are then digitised by a switched-capacitor Delta-Sigma Modulator (DSM), which employs energy-efficient inverter-based amplifiers that can operate from a sub-1V supply. To mitigate the effects of component mismatch and 1/f noise, dynamic error-cancellation techniques such as chopping, auto-zeroing and dynamic element matching are used in both the front-end and the DSM. After a 1-point temperature calibration, the sensor achieves a simulated inaccuracy of ±0.20oC (3σ) over temperatures ranging from -55oC to 125oC. From simulations, it does this while operating from a 0.9V supply and dissipating only 270nW. It occupies an estimated area of 0.09mm2 in a 180nm CMOS process. Compared to previous CB temperature sensors, this design occupies 2.8x smaller area and dissipates 3x less power.

This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves state-of-the-art energy efficiency. Realized in a standard TSMC 65nm CMOS technology, the modulator achieves 99.24dB SNR, 99.2dB SNDR and 100dB DR in a bandwidth of 24kHz while consuming only 80μW. This translates into the highest energy efficiency (FoMSNDR, 184dB) reported for a continuous-time delta-sigma modulator.

MEMS microphones offer a significant scope to improve miniaturization, integration and cost of acoustic systems, poised to be the preferred microphone option for consumer electronics and medical advancements. A MEMS microphone needs a readout interface to convert the microphone’s output to a digital code for further processing, while its poor driving ability poses a challenge on the design of readout ADCs.

In this thesis, the theory and implementation of a high input impedance continuous-time sigma-delta modulator (SDM) for a MEMS microphone readout is presented. A pseudo-virtual ground feedforward structure is used to eliminate the internal feedback DAC and contribute to enhanced linearization. To meet the requirement of high input impedance, a Gm-C first integrator is employed, featuring a resistive source degeneration structure and a local Gm-boosting loop to enhance the linearity of the first stage. For the second stage, a VCO-based integrator and quantizer are employed, offering advantages including inherent multilevel quantization and intrinsic clock-level averaging (CLA). The second order SDM consumes an estimated power of 57μW, achieving an 83dB SNR and a 79dB SNDR in simulation, reflecting its efficiency in audio applications.

Voltage references are an essential building block for many electronic systems, such as analog-to-digital and digital-to-analog converters, and voltage regulators. Although state-of-the-art voltage references already demonstrated high performance over the standard temperature range (−40 °C to 125 °C), specific applications require an operating temperature far beyond this range. A relevant example is the electronic interface for quantum processors, for which voltage references that can operate down to cryogenic temperatures are needed. This thesis presents a CMOS-based voltage reference that can work over a wide temperature range from 4K to 300K. To achieve a low-drift, high-accuracy reference, it is designed based on the devices’ cryogenic behaviour to minimize the nonlinearities of the PTAT- (proportional to absolute temperature) and CTAT (complementary to absolute temperature) voltages and combine them to generate a stable output voltage. Dynamic compensation techniques are employed to reduce the effect of process variations and a switched-capacitor circuit is proposed to minimize the output ripple. The targeted specifications of this design are comparable with the state-of-the-art voltage references working at room temperature. To verify the performance at cryogenic temperatures, the design has been taped out in 40nm CMOS technology.

In today's highly information-based society, portable smart devices are helping everyone all the time. At the same time, many of them need corresponding power management modules to provide them with stable power from the Li-ion battery. Since different functional modules require different voltage levels, a special DC-DC converter or driver must be designed to meet the requirements. In this thesis, one design is proposed to fulfill the requirement of high efficiency, and another one achieves fully integrated.

This thesis proposes a hybrid DC-DC step-up converter with a new architecture by merging a traditional inductor-based (IB) boost converter with a switched-capacitor (SC) converter to boost 3-4.2-V input to 20-30-V output. By serially connecting an IB boost converter and a 1:6 Dickson SC converter, the capacitors take over most of the output voltage stress. As a result, the voltage stress over each switch is limited to 5 V, which makes it possible to implement all the power switches with only on-chip 5-V devices. Thanks to the 5-V devices, the overall power conversion efficiency is improved in various aspects. The switching frequency of the SC stage is decreased by the soft charging technique, which helps further improve the efficiency. The proposed converter is designed and simulated in TSMC 0.18 um BCD process. An efficiency of 93.08 % is achieved under 3.7-V input and 29-V output voltage with a 25-mA current load.

A fully integrated VCSEL driver with adjustable pulse width is also proposed in this thesis. By combining two separate control signals, the VCSEL driver is able to overcome challenges posed by PVT and technology process limitations to achieve the narrowest pulse width of around 300-ps. The proposed converter is designed and simulated in SMIC 55 BCD process.

This article presents a novel wide operational range reconfigurable regulating rectifier for wireless power transfer. The proposed 1X/2X/3X rectifier achieves wide range voltage regulation without global loop control to minimize the area occupation. Compared with previous work, more working modes and greater magnification allow the proposed rectifier to regulate smaller signal, which extends voltage regulation range. A novel local loop control system is proposed for voltage rectification with three modes. The local loop adaptively senses the duty cycle of mode signal to determine which two working modes the rectifier should work with and configure the rectifier in these two modes. Then the rectifier are switching between two working modes according to the comparison result with reference voltage. Also, the change of which two working modes are also triggered by a window comparator to make sure the change happens when the output voltage is far away from reference voltage. The system is designed and simulated in a 0.18um BCD technology. The measurement results show that the proposed system can rectify wide-range input AC power to a regulated output. The achieved voltage conversion ratio (VCR) is 0.95-2.68 with a peak power conversion efficiency (PCE) of 87.4%.

The heart is one of our vital organs. It functions by periodically contracting in a rhythmic way. Sometimes, this rhythmic behaviour is affected by abnormalities in the tissue. These conditions are referred to as cardiac arrhythmias. One kind is of specific interest, called atrial fibrillation (AF). To further study AF, methods have been developed to estimate the conductivity of cardiac cells based on the measured electrical signals. In addition, other parameters of interest besides the conductivity are involved. The goal of this project was to consider one of the parameters in the electrogram (EGM) model: the sensor-to-cell height.
First, we studied the effect of the height as a parameter in the model when used for conductivity estimation. To that end, a detector was built with which we can explain the effect of all involved parameters on the ability to accurately estimate any parameters of interest.
In addition, we considered the case where the height is unknown and is estimated, thus possibly including estimation errors. The focus was on the consequences of making errors in the estimation of the height with respect to conduction block detection and conductivity estimation.
Lastly, the effort was made to estimate the height. Here, the optimisation problem of height estimation was formalised and derived as its implementable form. At first, a simplified EGM model was assumed in order to mimic and estimate cell-specific effects, i.e. the cell conductivities. Then, the height was estimated in various situations to study its behaviour and performance under different conditions. Then, also the standard EGM model was used in the same way, after which we also tested the performance of the designed algorithm in combination with existing conductivity estimation methods.

Due to the precise lithography and highly pure silicon used in IC technology, thermal-diffusivity (TD) temperature sensors can achieve high accuracy without the need for trimming. TD sensors employ electrothermal filters (ETFs) to measure the thermal diffusivity of silicon, i.e. the rate at which heat diffuses through silicon, which is a well-defined function of temperature. This thesis presents two approaches to improve the accuracy and resolution of TD sensors. The first approach investigates the effect of variations in ETF geometry on sensor resolution and proposes a multiplexing scheme to utilize a single readout circuit for reading out multiple ETFs. The second approach aims to investigate the effect of improvements in CMOS technology on sensor accuracy by scaling two ETFs to the 65nm process from the 180nm process. A first-order phase-domain delta-sigma modulator is designed for the readout of the ETFs in the 65nm process, and the previously designed multiplexing scheme is used for cost and time-efficient tape-out. Based on the estimated lithographic error of the 65nm process, the two ETFs are expected to achieve untrimmed inaccuracies of 0.18℃(3𝜎) and 0.36℃(3𝜎), respectively.

Class-D amplifiers are quickly becoming the standard in many audio applications. Their highly efficient behavior and wide power range make these amplifiers more suitable than traditional Class A/AB audio amplifiers. Battery-powered devices are a particularly interesting sub-field due to their special demand for extended battery duration and higher efficiency. An output power lower than 2 W, along with good performances in terms of linearity and efficiency, is often required. Many stand-alone Class-D Amplifiers have analog inputs, making them susceptible to interference that negatively impacts their behavior. This problem can be mitigated by employing an insensitive input digital interface. Many standard solutions often require complex architectures, which limit these systems' reliability. This work proposes a digital-input class-D amplifier with a multi-level output stage that, together with a relatively low (480 kHz) switching frequency, reduces idle power consumption while achieving good linearity. Based on a 180 nm BCD technology, it can drive a 16-Ω load showing pre-layout simulated performances: -111.3 dB THD+N, 115.6 DR, 91.4 % peak efficiency, and 2.14 mW idle power consumption.

Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of wires that can be placed between room temperature and the cryogenic chamber is limited, this creates a bottleneck in the scaling of quantum computers. Cryogenic CMOS (cryo-CMOS) electronics has been proposed to overcome this bottleneck. Operating the control electronics at cryogenic temperature, very close to the qubit, and controlling and reading out the qubits by frequency multiplexing relaxes the interconnect bottleneck. This work tackles this challenge by focusing on the qubit readout system and more specifically on the spin-qubit readout. The main target is to develop a cryo-CMOS analog-to-digital converter (ADC) for such an application. 
The readout of frequency multiplexed spin-qubits using RF reflectometry is considered the target application. The non-idealities of the RF-reflectometry scheme are simulated and analyzed for the qubit multiplexing and included in the system-level modeling of the readout chain. The target design specifications of the ADC are derived from such system-level simulations, resulting in the need for a 1 GSa/s ADC with ENOB > 6 bits operating at 4 K for the readout ~20 frequency-multiplexed spin-qubits with a BER of 1e-03.
Based on those specifications, this work proposes a 2-channel time-interleaved ADC using a Loop-Unrolled Successive Approximation Register (LU-SAR) ADC. The loop unrolling technique in combination with time-interleaving achieves the sampling rate of 1.1 GSa/s. The design includes the integration of a dynamic amplifier as an input driver and the generation of all required timing for the ADC core and the dynamic amplifier. Foreground calibration of the SAR comparator offset is included to achieve the linearity specifications. The ADC has been designed in TSMC 40nm CMOS technology and taped out for fabrication. After  calibration of comparator offset and calibration of the delay/gain mismatch between the two time-interleaved channels, the simulated performance of the ADC demonstrates an ENOB of 6.35 bits, SNDR of 40 dB, SFDR >50 dBc. The Figure-of-Merit of the designed ADC is 25.2 fJ/conv at 1 GSa/s sampling rate (including the driving amplifier and the clocking circuitry), which is significantly higher than the prior cryogenic ADCs and on-par with room-temperature state-of-the-art ADCs. The proposed ADC contributes towards the realization of future large-scale quantum computers, comprising million-qubit quantum processors integrated with cryogenic CMOS interface electronics.

A key issue in current quantum computing interfaces is the dense interconnect between electronics at cryogenic temperature (CT) and room temperature (RT). Recently, progress has been made to move more control electronics from RT to CT, reducing interconnect overhead. The next step towards minimal interconnect is a direct wireline interface between RT and CT. This work presents a full­rate 10 Gb/s clock­and­data recovery circuit for a high speed serial link receiver operating at CT.

A novel phase detector is utilized to reduce power consumption by removing the need for both a pulse generator at the input and, a buffer between the phase detector and voltage controlled oscillator. Additionally, a digital delay­locked loop is added to improve the retiming margin, achieving higher jitter tolerance. Implemented in 40­nm CMOS, post­layout simulation shows a core power consumption of 3.89 mW from a 1.1­V supply at 10 Gb/s, producing an rms­jitter of 84 fs and an estimated jitter tolerance
of 1.1 UIpp at 10 MHz.