This thesis describes the development of high-performance Class-D audio amplifiers, outlining their significance in modern audio systems. The primary aim is to reduce the system cost and size associated around Class-D amplifiers by minimizing the use of off-chip components, while ensuring high performance and audio fidelity.

Chapter 1 introduces audio amplifiers as integrated circuits, highlighting their role in amplifying electrical signals to drive loudspeakers in various applications. It outlines the key factors influencing amplifier design, including system cost and size, output power, efficiency, electromagnetic interference (EMI), and audio fidelity. The chapter briefly discusses two major classes of amplifiers- Class-AB and Class-D amplifiers (CDAs), particularly emphasizing the latter for high efficiency benefits on account of the switching output stage. Additionally, it introduces the two types of speakers that the amplifiers in this work are optimized to drive, the conventional electrodynamic speaker and the increasingly popular piezoelectric speaker. The discussion includes the advantages and disadvantages of each speaker type and how their electrical impedances impact amplifier design.

Chapter 2 delves into the architectural and circuit techniques used in modern CDAs, comparing different output stage topologies and modulation schemes, and their impact on high-frequency PWM energy and ripple current — key measures of the amplifier’s EMI performance. It introduces conventional AD / BD PWM modulation schemes, highlighting their high frequency PWM characteristics from DM and CM perspectives, before exploring more complicated multi-level and multi-phase architectures that aim to reduce the ripple content and EMI. The trade-offs between these modulation schemes in terms of EMI performance and component requirements are examined. It discusses the benefits of increasing the PWM switching frequency above the AM band ( 1.7MHz), which then allows for smaller and cheaper LC filters. Pulse-density modulation (PDM) using a 1-bit delta-sigma modulator (ΔΣM) is covered, emphasizing its benefits in terms of linearity and challenges related to wideband quantization noise and EMI. Lastly, the chapter also addresses the adaptability of CDAs for driving various speaker loads, particularly newer piezoelectric speakers, and discusses innovative techniques for damping LC resonance without external resistors, significantly reducing power consumption and system cost.

Chapter 3 outlines the development of a 28WCDA for automotive applications, employing a hybrid multibit ΔΣM-PWM scheme to achieve high linearity and low EMI in the AM band. The design features a fully-differential 3rd order loop filter, a multilevel non-uniform quantizer, and an H-bridge output stage that operates at a switching frequency above the AM band. This hybrid modulation technique addresses the limitations of 1-bit delta-sigma modulation, and significantly reducing out-of-band emissions while maintaining high linearity across a broad output power range thanks to the high-gain loop filter. The digital and analog circuits in this design, including the loop filter integrators and quantizer, are designed with low-voltage devices to ensure area and power efficiency. In contrast, the high-power output stage and driving circuits are built with more robust high-voltage devices. This prototype amplifier meets the stringent CISPR-25 EMI standards within the AM band using a relaxed LC filter, while also achieving high linearity, dynamic range, and supply rejection. Chapter 4 introduces a CDA that incorporates a dual voltage/current feedback (VFB/ CFB) topology, specifically designed to drive capacitive piezoelectric speaker loads without the need for external damping resistors. This dual-loop structure effectively mimics a series resistor in an LCR network, allowing for resistor-less LC resonance damping, thereby reducing cost, size, and power consumption. Load current sensing, used in the CFB path, is implemented using purely low-side on-chip sense resistors, thereby avoiding high-frequency switching issues and simplifying the readout network. This low-side sensing is feasible due to the push-pull modulation scheme, which is advantageous for a low-power design. Techniques such as CFB filtering and chopping are employed to reduce non-idealities like noise and non-linearity in the feedback paths. The prototype, fabricated in a 180 nm BCD process, can drive a 4 μF load with a peak current of 4.4 A and achieves an idle power consumption of 122 mW. Measurement results confirm the system’s efficacy in damping LC resonance and maintaining high performance, with significant power savings compared to traditional designs using external resistors.

Chapter 5 builds upon the dual feedback architecture introduced in Chapter 4 by incorporating a quadrature chopping scheme to further enhance the linearity and noise performance of Class-D amplifiers. This technique addresses timing skew issues between low-voltage input choppers and high-voltage output choppers, which can degrade signal linearity and increase noise. The quadrature chopping scheme dynamically matches the timing of the choppers, resulting in significant improvements in large-signal total harmonic distortion (THD) and a reduction in noise foldback into the audio band. The chapter presents measurement results that demonstrate the extension in the linear output of the amplifier to close to 95% the full-scale.

Chapter 6 concludes the thesis by summarizing the key findings and contributions of the research. It highlights the original contributions, including the hybrid PWM-DSM modulation scheme, the dual feedback topology for resistor-less damping of capacitive piezoelectric speaker loads, and the quadrature chopping scheme for further improved linearity and noise performance. The chapter also discusses potential future research directions, such as further optimization of EMI performance through advanced modulation techniques, improved current sensing methods, and enhanced feedback accuracy.
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Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (?SM) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 µm technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of µWs.

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This paper presents a Class-D piezoelectric speaker driver that employs a quadrature feedback chopping scheme (QCS). Compared to a conventional single feedback chopping scheme (SCS), the use of QCS can eliminate the timing skew between low-voltage (LV) and high-voltage (HV) choppers, greatly improving large-signal linearity. A prototype implemented in a 180nm BCD process achieves a peak THD+N of 88dB/-92.5dB for a 1kHz/6kHz input frequency and 37μ VR MS output noise (A-weighted) while driving a 4μ F load. Thanks to QCS, the large-signal THD+N has been improved by 29 dB, while the output voltage swing achieving -60dB THD+N has been extended from 86.9% to 99.5% of the full-scale (FS).

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Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in televisions, laptops, etc. Such speakers can be modelled as a large capacitive load, and so are typically driven by a Class-AB amplifier via a series resistor that ensures driver stability, and limits load current, but wastes power [1], [2]. In [3], the Class-AB amplifier is replaced by a more power-efficient Class-D amplifier (CDA) in series with an additional inductor. However, a series resistor is still required to damp the resulting LC resonant circuit, which could otherwise draw excessive currents when excited by large-signal distortion (e.g. clipping) harmonics around the LC resonance frequency. Alternatively, by using a feed-forward architecture based on LC filter diagnostics to limit overshoot currents, the series resistor can be replaced by a second inductor, at the expense of increased system complexity and cost [4].@en

This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm2, achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 μW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoMSNDR of 182.7 dB.

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This article presents a Class-D audio amplifier for capacitive piezoelectric speaker loads. Employing a dual voltage feedback (VFB)/current feedback (CFB) topology, the amplifier is capable of damping LC resonance without using an external damping resistor, therefore reducing system power consumption, cost, and size. Additional power savings are achieved by using a push–pull (PP)-modulated output stage. To mitigate linearity degradation due to the mismatch of the feedback resistors, they are dynamically matched by employing choppers. The prototype, taped out in a BCD 180-nm process, can drive up to 4 μ F load with a peak current of 4.4 A while achieving an idle power consumption of 122 mW and a peak THD + N of − 91 dB.@en

In chopper amplifiers, the interaction between the input signal and the chopper clock can give rise to intermodulation distortion (IMD). This chopper-induced IMD is mainly due to amplifier delay, which causes large pulses at the output of the amplifier's output chopper. This article proposes the use of a so-called fill-in technique to eliminate these pulses, and thus the resulting IMD, by multiplexing the outputs of two identical amplifiers that are chopped in quadrature. A prototype chopper-stabilized amplifier was implemented in a 180-nm CMOS process. Measurements show that the fill-in technique suppresses chopper-induced IMD by 28 dB, resulting in an IMD of -126 dB for input frequencies near 4 F_CH (=80 kHz). It also improves the amplifier's two-tone IMD (with 79 and 80 kHz inputs) from -97 to -107 dB, which is the same as that obtained without chopping.@en

Amplifiers often employ chopping to achieve low offset and low-frequency noise. However, the interaction between the input signal and the chopper clock can cause chopper-induced intermodulation distortion (IMD) [1] -[5]. This is especially problematic for input frequencies (Fin) near even multiples of the chopping frequency (FCH), as the resulting IMD tones fold-back to low frequencies and so cannot be filtered out. In [2] -[4], spread-spectrum clocks are used to convert such tones into noise-like signals. However, this increases the noise floor and does not address the underlying problem. This paper shows that chopper-induced IMD is mainly due to amplifier delay, which results in large chopping spikes. A novel fill-in technique is proposed that mitigates these spikes, and so reduces the chopper-induced IMD. In a prototype chopper-stabilized amplifier, it reduces the chopper-induced IMD by 28dB, resulting in an IMD of -126dB for input frequencies near 4FCH (=80kHz). Similarly, it improves the chopped amplifier's two-tone IMD (79 and 80kHz) from -97dB to -107dB, thus maintaining the same IMD as the un-chopped amplifier.

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This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm2 in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

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This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of -107.8 dB/-102 dB and a peak efficiency of 91%/87% with 8- and 4-Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.

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Class-D amplifiers are often used in high-power audio applications due to their high power efficiency. They typically employ pulse-width modulation (PWM) at a fixed carrier frequency, which may cause electromagnetic interference (EMI). Setting this frequency f_PWM) below the AM band (535 to 1605kHz) helps mitigate this, but its harmonics still contain substantial energy and must be filtered out by bulky LC filters with low cut-off frequencies (f_c = 20 to 40 kHz), significantly increasing system cost and size. Stability considerations also constrain the amplifier's unity-gain frequency to be < mathrm{f} {mathrm{PWM}}/pi [1], compromising the audio-band loop gain required to suppress output-stage nonlinearity. Setting f_PWM above the AM band helps increase f_c and allows a higher loop gain [2]. However, this results in narrower pulses at higher power levels (higher modulation index), which cannot be faithfully produced by the output stage, thus exacerbating its non-linearity. Delta-sigma modulation (DeltaSigma M) has fixed pulse widths and does not suffer from these narrow-pulse artefacts. However, the out-of-band noise of 1bit modulators then requires larger LC filters. Moreover, high-order loop filters must be used to achieve sufficient SQNR, which then require additional techniques to maintain stability as the modulation range approaches 100% [3].

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This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ Σ M-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4- Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.

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This paper describes a class-D audio amplifier with a multilevel output stage that reduces both EMI and idle power. High loop gain, and thus high linearity, are enabled by a relatively high (4.2 MHz) switching frequency, which relaxes the requirements on its output LC filter. Fabricated in a 180nm BCD technology, it can drive 14 W into an 8-Ω load with state-of-the-art performance: -107.8 dB THD+N, 91% peak efficiency, and 7 mA quiescent current. It meets the CISPR 25 Class 5 radiated emission standard with a low-cost 580 kHz LC filter, improving the state-of-the-art by 5.8x.

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This paper presents a discrete-time (DT) zoom ADC for audio applications. A 2b quantizer in combination with a low power “fuzz” suppression technique, results in a significant improvement in linearity and energy-efficiency over previous designs. The ADC occupies 0.27mm 2 in 0.16μm CMOS and consumes 440μW from a 1.8V supply. In a 20kHz BW, it achieves 109.8dB DR and 106.5dB SNDR, resulting in a state-of-the-art Schreier FoM of 186.4dB.@en

This article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm ² and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 \mu \text{W}. This results in a Schreier figure of merit (FoM) of 183.6 dB.

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This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &#x0394; &#x03A3; ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-&#x03BC;m CMOS process, the prototype occupies 0.26 mm&#x00B2; and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 &#x03BC;W. This results in a Schreier figure of merit (FoM) of 185.8 dB.

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Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.

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