This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm2, achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 μW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoMSNDR of 182.7 dB.

@en

This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm2 in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

@en

Analog-to-digital converters (ADCs) are an indispensable part of the digital age we are living in, as they form the interface between physical reality and virtual reality. Higher ADC energy efficiency is the dominant focus of ADC design research due to the high impact of ADC energy consumption to total energy consumption of the systems they are employed in. The energy consumption of an ADC increases with its resolution within a given signal bandwidth, which makes the efficiency of high-resolution ADCs even more important. Although the average energy efficiency of ADCs improved orders of magnitude in the last two decades, the high energy consumption of high-resolution ADCs was still restrictive for a large range of applications. This thesis investigates how the zoom ADC architecture can achieve both high resolution and high energy efficiency.@en

This paper presents a discrete-time (DT) zoom ADC for audio applications. A 2b quantizer in combination with a low power “fuzz” suppression technique, results in a significant improvement in linearity and energy-efficiency over previous designs. The ADC occupies 0.27mm 2 in 0.16μm CMOS and consumes 440μW from a 1.8V supply. In a 20kHz BW, it achieves 109.8dB DR and 106.5dB SNDR, resulting in a state-of-the-art Schreier FoM of 186.4dB.@en

This article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm ² and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 \mu \text{W}. This results in a Schreier figure of merit (FoM) of 183.6 dB.

@en

This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 ×m CMOS process, occupies 0.27 m m² and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 ×W. This results in a state-of-the-art Schreier FoM of 183.6 dB.

@en

Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.

@en

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &#x0394; &#x03A3; ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-&#x03BC;m CMOS process, the prototype occupies 0.26 mm&#x00B2; and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 &#x03BC;W. This results in a Schreier figure of merit (FoM) of 185.8 dB.

@en

This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.@en

This paper discusses the use of chopping in continuous-time sigma-delta modulators where 1/f noise and offset need to be suppressed by continuous-time methods. An intuitive analysis of the artifacts related to chopping is presented. Aliasing of quantization noise is found to be the main problem, especially for chopping frequencies lower than the modulator's sampling frequency (fs). Correctly timed return-to-zero and switched-capacitor DACs are proposed as a solution to the aliasing problem. In both cases, the key idea is to synchronize DAC transitions with moments when the quantization noise at the input of the first integrator is low. Circuit level simulations are presented to validate the proposed techniques.@en

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm² in the 0.16- μm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

@en

Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ΔΣ ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ΔΣ conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.@en