This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors with different TCs. In this work, such a network is used to realize a temperature-dependent reference voltage whose TC cancels that of a single-resistor RC time constant. Compared with the conventional approach, which requires resistors with TCs of opposite polarity, the proposed approach can be implemented with resistors with TCs of similar polarity, and so it can be implemented in most CMOS processes. To compensate for RC spread, a trimmed capacitor is used to adjust the nominal frequency. Two prototype chips were made, one based on p- /n-polysilicon resistors and other based on silicided/p-diffusion resistors. Fabricated in a standard 180-nm CMOS technology, the polysilicon-based prototype has an active area of 0.01 mm2 and an absolute inaccuracy of ±2800 ppm from -45 °C to 125 °C with a fixed TC-trim and a one-point frequency trim. After one week of accelerated aging at 150 °C, however, significant drift (5000 ppm) was observed. The diffusion-based prototype exhibits greater inaccuracy (±14 400 ppm) but much less drift (600 ppm).

Recently, rapid strides have been made in improving the accuracy of RC-based frequency references [1 -3]. Inaccuracies better than \pm 500ppm from -45^{\circ}C to 85^{\circ}C have been achieved, but typically at the expense of a costly and time-consuming 2-point trim to compensate for RC spread and temperature dependence. This paper describes a 16MHz RC-based frequency reference that achieves \pm 400ppm inaccuracy over the industrial temperature range with a single room-temperature (RT) trim. The prototype draws 88\muA from a1.8V supply and occupies 0.14mm^{2}, which represents a 2\times improvement in both power and area compared to the state of the art [2].

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This article reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing Δ Σ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on Δ Σ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.

This article describes a high-performance capacitance-to-digital converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5-dB SNR in a 1-ms conversion time. With a sensing O 8-mm probe and a 25μm stand-off distance from the target, it achieves 0.18-nm resolution. Moreover, it offers an in-band common-mode rejection ratio (CMRR) higher than 117 dB, providing decent electric field interference immunity.

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CTM). By exploiting the CCIA’s ability
to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and
thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa (1) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by 80× over a 50 °C range.

This paper presents a readout IC that uses an asynchronous capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. A power-efficient tracking algorithm ensures that the CDC consumes negligible power consumption in the absence of touch events. To facilitate its use in wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low-power relaxation oscillator. At a 38-Hz scan rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.

This paper presents an overview of energy-efficient analog-to-digital converters (ADCs) specifically intended for the readout of Wheatstone bridge sensors. Apart from achieving good energy-efficiency, such bridge-to-digital converters (BDCs) must achieve low input-referred offset, drift and noise; high gain accuracy, stability and linearity; as well as high immunity to power-supply and common-mode variations. Various BDC architectures are discussed, beginning with traditional designs, in which an instrumentation amplifier is used to drive an ADC, and moving on to more recent work, which attempt to increase energy efficiency and reduce complexity by eliminating the instrumentation amplifier. The performance of these topologies, and in particular their energy-efficiency, will be compared and summarized.

This paper presents a readout IC that uses an asynchronous charge-redistribution-based capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. Thanks to the power efficient tracking algorithm, the CDC consumes negligible power consumption in the absence of touch events. To facilitate stand-alone or wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low power relaxation oscillator. At a 38 Hz scan-rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.

This paper describes a high-performance Capacitance-to-Digital Converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5dB SNR in a 1ms conversion time, which is 34 times more energy-efficient than the prior art. Moreover, it also offers a 117dB in-band (1kHz) Common-mode Rejection Ratio (CMRR), providing decent electric field interference immunity.

Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].