Resin-reinforced Ag sintering materials represent a promising solution for die-attach applications in high-power devices requiring enhanced reliability and heat dissipation. However, the presence of resin and intricate microstructure poses challenges to its thermal performance, and improvement strategies remain unclear. This work utilizes 3D FIB-SEM nanotomography to reconstruct the microstructure of this material under various process conditions. The analysis reveals that, even with an Ag volume fraction as low as 47.3%, Ag particles form a robust 3D network. Geometric tortuosity quantifies the effect of different sintering conditions on the Ag particle network in all spatial directions. Effective thermal conductivity is simulated based on realistic microstructure models. Results show a significant negative correlation between tortuosity and effective thermal conductivity. Increasing sintering temperature in Model B notably reduces tortuosity and enhances effective thermal conductivity. Sensitivity analysis underscores the dominant role of Ag volume fraction in regulating effective thermal conductivity. Finally, transient thermal impedance measurement of this material as a thin die-attach layer in actual high-power devices demonstrated its application potential. This article strives to explore the relationship between process, microstructure, and thermal properties of this material to provide a reference for further development.

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The ability to accurately predict the reliability and lifetime of electronics is of great importance to the industry. The failure of the solder joint is of particular interest for these predictions, because of their susceptibility to failure under thermo-mechanical stress. However, the experimental or even conventional simulation techniques employed to estimate the lifetime of a solder joint are often too expensive or time consuming to be of practical use. Therefore, this work introduces a physics-informed Long Short-Term Memory (LSTM) to predict the plastic strain in the critical area of the solder joint. The predicted values are in agreement with the values gained from finite elements, thereby demonstrating the advantage of applying the proposed methodology.@en

Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

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Model order reduction techniques are developed and utilized to make numerical simulations more efficient. The use of Reduce Order Models (ROM) also enables data exchange with external parties without disclosing the sensitive information present in a Full-Order Model (FOM). It is crucial to optimize for both the efficiency and accuracy of a ROM to keep a minimal deviation from the FOM. The complexity of a ROM-based simulation depends on the definition of the ROM as well as its connection with the remaining FOM. This paper investigates the effect of different ROM-FOM interface definitions for a test case consisting of an electronic package-on-PCB assembly. A virtual Design of Experiments (DoE) was carried out with a total of 41 cases considering three different locations and up to four different constraint equations for the ROM-FOM interface. The effect on the accuracy and time-efficiency of the ROM-based thermomechanical simulations are compared with respect to the full Finite Element (FE) model. The deformable configuration for the interface generally showed the most accurate results, while the rigid configuration was the most efficient across the board. The beam configuration did not always follow an expected trend based on the order of elasticity values of the assigned materials. Based on the deformation results and the time associated with ROM generation and use-pass, multiple optimal solutions from the DoE are discussed.@en

Lifetime analyses are crucial for ensuring the durability of new Light-emitting Diodes (LEDs) and uncertainty quantification (UQ) is necessary to quantify a lack of usable failure and degradation data. This work presents a new framework for predicting the lifetime of LEDs in terms of lumen maintenance, effectively quantifying the natural variability of lifetimes (aleatory) as well as the reducible uncertainty resulting from data scarcity (epistemic). Non-parametric survival models are employed for UQ of low-magnitude failures, while a new parametric interval prediction model (IPM) is introduced to characterize the uncertainty in high-magnitude lumen depreciation events and long-term extrapolated lifetimes. The width of interval-valued predictions reflects the inherent variability in degradation paths whilst the epistemic uncertainty, arising from data scarcity, is quantified by a statistical bound on the probability of the prediction errors for future degradation trajectories. A modified exponential flux decay model combined with the Arrhenius equation equips the IPM with physical information on the physics of LED luminous flux degradation. The framework is tested and validated on a novel database of LED degradation trajectories and in comparison to well-established probabilistic predictors. The results of this study support the validity of the proposed approach and the usefulness of the additional UQ capabilities.

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A significant challenge in the implementation of health monitoring systems for estimating the health state of devices is the lack of accurate information about design details. This challenge is particularly prominent in the field of power electronics, where both IC designers and converter designers are often hesitant to share information about their designs. Addressing this issue, this paper introduces a novel AI-driven digital twin modeling methodology that enables the detection and classification of failures in power semiconductors, particularly Wide Band Gap semiconductors. By employing AI-based system identification techniques, this method offers a noninvasive approach to health monitoring of power switches with high resolution, even while operating under real conditions. The proposed method has been validated by simulating wire bond failure in a SiC power MOSFET using MATLAB SIMULINK, and the results demonstrate its accuracy.

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In this article, we provide a comprehensive review of defect formation at the atomic level in interfaces and gate oxides, focusing on two primary defect types: interface traps and oxide traps. We summarize the current theoretical models and experimental observations related to these intrinsic defects, as they critically impact device performance and reliability. By integrating theoretical insights with experimental data, this review provides a thorough understanding of the atomic-scale interactions that govern defect formation.

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Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

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Abstract-Prognostic monitoring of Power QFN packages with four distinct silver pastes, each varying in material composition (pure-Ag and resin-reinforced hybrid-Ag) and sintering processes (pressure-assisted and pressureless), was investigated in this study. The PQFN packages with silver sintered die-attach materials were subjected to thermal cycling tests (-55 to 150&#x00B0;C), and the performance degradation was evaluated based on the following metrics: (i.) Electrical on-state resistance R_DS monitored periodically at specific thermal cycling intervals, and (ii.) Transient thermal impedance Z_th(t=0.1 s) monitored online during thermal cycling. These measurements were further validated using acoustic microscopy imaging and cross-sectional inspection. The pressureless Ag-sintering material demonstrated comparable performance to pressure-assisted Ag-sintering, with a dense microstructure, and consistent electrical and stable thermal performance. Whereas the pressureless resin-reinforced hybrid-Ag material exhibited degradation with a relative increase of ~33% in R_DSon, ~38% in Z_th(t=0.1 s), and ~67% delamination of the die-attach interface over 1000 cycles. These findings suggest that pressureless Ag-sintering may offer a viable alternative to pressure-assisted methods for Pb-free die-attachments, while resin-reinforced hybrid-Ag requires further development for improved thermo-mechanical reliability.

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The introduction of silicon carbide(SiC) has reduced the superiority of traditional silicon-based power module pack-aging strategies. As packaging strategies become increasingly complex, classical thermal modelling tools often prove inadequate in balancing efficiency with accuracy. Integrating these tools with machine learning (ML) can significantly enhance their application potential. This discussion commences by addressing the pressing issues in thermal modelling of SiC modules, specifically the challenges associated with multiple heat sources and heat spreading. During the design stage, ML models can swiftly simulate the thermal response of various packaging strategies, aiding engineers in eliminating ineffective options. In the monitoring phase, the employment of a digital twin enables a deeper investigation into degradation phenomena. This article reviews the current status and explores the potential applications of ML in thermal modelling of SiC power modules.

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Silver sintering offers a promising landscape for Pb-free die attachment in electronics packaging. However, the sintered interface properties are highly process-dependent and deviate from bulk silver properties. Conventional measurement methods do not adequately capture the die-attach application geometry. Hence, this study introduces a novel methodology for characterizing thin bond-line interfaces with high-conductive materials. The transient heat flux impedance ΔZth(t, Δx) was measured between two thermally sensitive devices interconnected using pressureless Ag-sintering material. A correction factor was derived, based on thermal half-space principles, to account for non-uniform heat spreading over the die-attach interface. Experimental findings estimate an effective conductivity of ∼115W/mk for the pressureless Ag-sintered interface. The measurement results were validated by measuring a SAC305 soldered interface, which exhibited ∼55 W/mK, and a non-conductive epoxy interface of ∼2.5 W/mK. Voids on the die-attach layer, resulting from material processing, were identified to influence the interface thermal behavior. An uncertainty analysis was further discussed, emphasizing equipment tolerances, measurement sensitivity, and geometrical and thermal anisotropies. The article concludes with a comparative summary of the proposed methodology against conventional methods, highlighting differences in working principle, thickness range, measurement parameters, and their advantages and limitations.@en

Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide-semiconductor capacitors, providing insight into how capacitance and conductance change during C-V measurements under conditions of high temperature, varied frequency, and varied applied voltage.@en

A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

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The various application scenarios of triboelectric nanogenerator (TENG) have attracted increasing research interest, while one of the biggest challenges is the energy extraction efficiency. Due to the small and time-varying inherent capacitor in a TENG, the previous energy extraction techniques e.g., full-bridge rectifier (FBR) and bias-flip (BF) rectifier, performed not well. To extract more energy from TENG, this article proposed a fully integrated switched-capacitor (SC) rectifier with an electrostatic charge boosting (ECB) technique, achieving simultaneous extraction from the synchronized triboelectric energy and self-excited electrostatic energy. The proposed rectifier was fabricated in a 180-nm BCD process. With the proposed ECB technique, the theoretical analysis and measurements show a quadratically increasing output power with respect to the rectification voltage, attaining a constant maximum power point (MPP) at the breakdown voltage of the circuit. A maximum output power of 127.6 μ W is measured with a TENG fabricated in-house. Compared to a passive FBR, the proposed rectifier enhances the output power by 14 times.

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The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this backdrop, machine learning technologies emerge as dynamic tools for correlation building and classification, revolutionizing the traditional approaches to design, manufacturing, and testing in electronic packaging, as well as the Design for Reliability (DfR) methodologies.This paper reviews the most recent AI-assisted approach for electronic packaging and then focuses on the AI-assisted DfR (AI-DfR) approaches. Our examination reveals that AI methods have been adapted to meet the specific needs of electronic packaging. The industry’s anticipation for AI-DfR stems from its potential to address prevailing reliability design challenges, yet its multidisciplinary essence poses hurdles to swift progress. This review proposes future directions for AI-DfR’s development, spotlighting critical areas such as the quality and efficiency of finite element modeling, design and optimization of training models, selection of AI models, and maintenance and value enhancement strategies.@en

This study introduces a training protocol utilizing Convolutional Neural Networks (CNNs) and Confocal Scanning Acoustic Microscopy (CSAM) imaging techniques to classify Power Quad Flat No-leads (PQFN) package delamination. The investigation involves empty PQFN packages with varied substrate metallizations subjected to thermal cycling. Four delamination classes were labeled: Die-pad delamination (Class-A), Bond-pad delamination (Class-B), both Die-pad and Bond-pad delamination (Class-C), and No delamination (Class-D). Due to data imbalance, additional randomness was introduced for distribution balancing. Residual Networks (ResNet-18) based CNN model was selected for classification. Five-fold cross-validation assessed overfitting performance concerning input data size, image resolution, and batch size. The ResNet-18 prediction performance was evaluated using precision and recall metrics, with the model achieving average precision and recall scores of 0.86/1 and 0.83/1, respectively. Additionally, a comparison of delamination among different substrate metallizations was presented with Ag and NiPdAu indicating significant delamination compared to bare Cu substrate. This study pioneers the integration of CNNs with CSAM imaging for package defect detection and classification, laying the groundwork for future research to address the complex interplay of multiple failure mechanisms in functional packages.@en

Digital Twins (DT) play a key role in Industry 4.0 applications, and the technology is in the process of being mature. Since its conceptualisation, it has been heavily contextualised and often misinterpreted as being merely a virtual model. Thus, it is crucial to define it clearly and have a deeper understanding of its architecture, workflow, and implementation scales. This paper reviews the notion of a Digital Twin represented in the literature and analyses different kinds of descriptions, including several definitions and architectural models. A new fit-for-all definition is proposed which describes the underlying technology without being context-specific and also overcomes the pitfalls of the existing generalised definitions. In addition, the existing three-dimensional and five-dimensional models of the DT architecture and their characteristic features are analysed. A new simplified two-branched model of DT is introduced, which retains a clear separation between the real and virtual spaces and outlines the latter based on the two key modelling approaches. This model is then extended for condition monitoring of electronic components and systems, and a hybrid approach to Prognostics and Health Management (PHM) is further elaborated on. The proposed framework, enabled by the two-branched Digital Twin model, combines the physics-of-degradation and data-driven approaches and empowers the next generation of reliability assessment methods. Finally, the benefits, challenges, and outlook of the proposed approach are also discussed.@en

Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150°C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (i.e., the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150°C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation.@en

This article introduces an online condition monitoring strategy that utilizes a transient heat pulse to detect package thermal performance degradation. The metric employed is the temperature-dependent transient thermal impedance "Zth(t, Tamb)."The proposed methodology offers quantitative insights into package thermal performance degradation and effectively pinpoints the presence of multiple failure mechanisms. A thermal test chip assembled in a power quad flat no-lead package is used in this study to demonstrate the methodology. The packaged devices are first characterized to determine the transient pulse duration, a critical parameter to monitor a specific region of interest. Subsequently, package thermal performance degradation is continuously monitored online during thermomechanical cycling lifetime experiments. The validity of the measurement results is later confirmed through acoustic imaging and cross-sectional analysis. The changes observed in Zth(t, Tamb) over thermal cycling correspond to the delamination of the active metal layers on the die and cohesive failure on the die attach. This article further includes a comparative summary, highlighting the distinctions between the proposed and industry-standard test methods. In conclusion, the importance of online condition monitoring to detect early signs of failure is emphasized, and the proposed methodology s practical applicability in real-life scenarios is briefly discussed.

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