Developing reliable and efficient power semiconductors is essential to realizing a sustainable future. Packaging materials for high-power applications are electrically overstressed, are exposed to harsh environmental conditions, and are subjected to heightened temperature swings, thereby compromising the device’s stability and longevity. In this dissertation, a series of experimental methodologies were explored for monitoring the package conditions, particularly the die-attach interface, which transmits the necessary electrical, thermal, and mechanical signals from the device to the system. Furthermore, advanced thermal management strategies were investigated to circumvent concentrated microthermal hot spots and improve the device’s power rating.@en

Board-level reliability (BLR) looks at the reliability problem in the package and PCB interconnection, which is an important topic in microelectronics. The current criterion in the BLR test is to look if the connection is open, which can only detect the failure and there is no available method that can detect the degradation of the solder joints. This project mainly focuses on the degradation process of solder joints in board-level vibration tests and thermal cycle tests.

Special methods and test programs are developed tailored for two test vehicles, and some of the test results are collected and analyzed. Assisted by the failure analysis technique, the physical change of solder joints can be observed.

Findings in this study show the parameter shift during the solder joint degradation and also the mathematic model that describes the relationship between the crack of the solder joints and resistance increment.

Wirebonding is an interconnection technology used to connect a chip to its LED package. It is currently not well understood which wirebond characteristics are best to tailor to prevent the failure of wirebonds. The focus of this thesis is to understand the physics-of-failure of wirebonds via an experimental approach. Therefore, an experimental setup is designed which can accurately measure the resistance of the wirebond samples by four-wire resistance measurements. Furthermore, Finite Element simulations are done to understand the physical nature of wirebond failure better.

Gold wirebonds with different loop geometries have been designed and made which are then subjected to temperature cycling. It is found through 4-wire experimental resistance setup that when a significant increase in resistance is reported, wirebond fatigue is imminent. Coffin-Manson based Finite Element
simulations show that stresses at the neck are higher than at the heel. In retrospect, when the wirebond samples are encapsulated in Silicone, there is an increase in the stresses at the heel.