This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

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Solder fatigue is a key failure mode in the electronic industry. Monitoring the actual degradation of the solder under real-time conditions in any application would be extremely beneficial. In this chapter, we describe the combination of experimental material characterization with numerical finite element (FE) simulations to obtain a prognostics and health monitoring (PHM) methodology for LED drivers used in outdoor lighting applications. Experimental characterization of a new type of solder is described. A FE model is created of a typical component in electronic drivers. The calculated damage level and the collected life data correlate together and form a model for predicting the lifetime of the drivers at certain user condition. The developed PHM methodology helps in identifying and reporting the failure of the driver in real time or can be used for predicting the actual remaining useful life (RUL).

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The ability to accurately predict the reliability and lifetime of electronics is of great importance to the industry. The failure of the solder joint is of particular interest for these predictions, because of their susceptibility to failure under thermo-mechanical stress. However, the experimental or even conventional simulation techniques employed to estimate the lifetime of a solder joint are often too expensive or time consuming to be of practical use. Therefore, this work introduces a physics-informed Long Short-Term Memory (LSTM) to predict the plastic strain in the critical area of the solder joint. The predicted values are in agreement with the values gained from finite elements, thereby demonstrating the advantage of applying the proposed methodology.@en

This article introduces an online condition monitoring strategy that utilizes a transient heat pulse to detect package thermal performance degradation. The metric employed is the temperature-dependent transient thermal impedance "Zth(t, Tamb)."The proposed methodology offers quantitative insights into package thermal performance degradation and effectively pinpoints the presence of multiple failure mechanisms. A thermal test chip assembled in a power quad flat no-lead package is used in this study to demonstrate the methodology. The packaged devices are first characterized to determine the transient pulse duration, a critical parameter to monitor a specific region of interest. Subsequently, package thermal performance degradation is continuously monitored online during thermomechanical cycling lifetime experiments. The validity of the measurement results is later confirmed through acoustic imaging and cross-sectional analysis. The changes observed in Zth(t, Tamb) over thermal cycling correspond to the delamination of the active metal layers on the die and cohesive failure on the die attach. This article further includes a comparative summary, highlighting the distinctions between the proposed and industry-standard test methods. In conclusion, the importance of online condition monitoring to detect early signs of failure is emphasized, and the proposed methodology s practical applicability in real-life scenarios is briefly discussed.

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Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide-semiconductor capacitors, providing insight into how capacitance and conductance change during C-V measurements under conditions of high temperature, varied frequency, and varied applied voltage.@en

This paper introduces an ontology-based Digital Twin (DT) architecture for the lighting industry, integrating simulation models, data analytics, and visualization to represent luminaires. The ontology standardizes luminaire components, facilitating interoperability with design tools. The calculated ontology-level metrics suggest mid-level complexity with Size Of Vocabulary (SOV) at 37, Edge-to-Node Ratio (ENR) at 0.865, Tree Impurity (TIP) at 0, and Entropy Of Graph (EOG) at 2.61. A use case explores the utility of the ontology in the design phase across two different geographical locations, assessing environmental adaptability. The ontology captures opto-thermo-electric interactions, providing insights into luminaire performance. Results from inflating the DT and conducting simulations align with existing literature, indicating a degradation of around 12% over 8 years on the radiant flux. This ontology, up to the authors’ knowledge, is the first formal definition for the lighting industry, aiming to encompass the entire luminaire lifecycle. The current focus is on design and operational phases, with potential future enhancements to include real-time monitoring for performance evaluation and predictive maintenance. This work contributes to luminaire analysis and supports the development of sustainable lighting solutions in the industry.

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The increasing awareness of environmental concerns and sustainability underlines the importance of energy-efficient systems, renewable energy technologies, electric vehicles, and smart grids. Hence, stringent constraints and safety regulations have been prompted to meet reliability standards in power electronics. This chapter provides a comprehensive outlook on the current state of power semiconductor devices, field-critical applications, dominant degradation mechanism (chip-related and package-related), and the emerging measurement techniques for reliability/condition monitoring. This chapter delves into the underlying physics behind each reliability measurement method reviewed. A comparative summary of cost, complexity, online monitoring capability, accuracy, and intrusiveness is provided to enable readers to make informed decisions about the measurement methods. This chapter emphasizes the significance of early fault detection through online monitoring, as it can effectively reduce system downtime for seamless non-interruptive operation.

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Industrial assembly lines are the heartbeat of modern manufacturing, where precision and efficiency are paramount. This paper introduces a novel hybrid Explainable artificial intelligence (XAI) approach to enhance monitoring and analysis in industrial assembly. By fusing the power of vision anomaly detection models with the clarity of the gradient tree boosting algorithm, this framework not only boosts defect detection accuracy but also provides transparent, actionable insights. This synergy transforms how operators and engineers interact with AI, fostering trust and enhancing operational excellence.

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Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

The introduction of silicon carbide(SiC) has reduced the superiority of traditional silicon-based power module pack-aging strategies. As packaging strategies become increasingly complex, classical thermal modelling tools often prove inadequate in balancing efficiency with accuracy. Integrating these tools with machine learning (ML) can significantly enhance their application potential. This discussion commences by addressing the pressing issues in thermal modelling of SiC modules, specifically the challenges associated with multiple heat sources and heat spreading. During the design stage, ML models can swiftly simulate the thermal response of various packaging strategies, aiding engineers in eliminating ineffective options. In the monitoring phase, the employment of a digital twin enables a deeper investigation into degradation phenomena. This article reviews the current status and explores the potential applications of ML in thermal modelling of SiC power modules.

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Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

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A significant challenge in the implementation of health monitoring systems for estimating the health state of devices is the lack of accurate information about design details. This challenge is particularly prominent in the field of power electronics, where both IC designers and converter designers are often hesitant to share information about their designs. Addressing this issue, this paper introduces a novel AI-driven digital twin modeling methodology that enables the detection and classification of failures in power semiconductors, particularly Wide Band Gap semiconductors. By employing AI-based system identification techniques, this method offers a noninvasive approach to health monitoring of power switches with high resolution, even while operating under real conditions. The proposed method has been validated by simulating wire bond failure in a SiC power MOSFET using MATLAB SIMULINK, and the results demonstrate its accuracy.

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Model order reduction techniques are developed and utilized to make numerical simulations more efficient. The use of Reduce Order Models (ROM) also enables data exchange with external parties without disclosing the sensitive information present in a Full-Order Model (FOM). It is crucial to optimize for both the efficiency and accuracy of a ROM to keep a minimal deviation from the FOM. The complexity of a ROM-based simulation depends on the definition of the ROM as well as its connection with the remaining FOM. This paper investigates the effect of different ROM-FOM interface definitions for a test case consisting of an electronic package-on-PCB assembly. A virtual Design of Experiments (DoE) was carried out with a total of 41 cases considering three different locations and up to four different constraint equations for the ROM-FOM interface. The effect on the accuracy and time-efficiency of the ROM-based thermomechanical simulations are compared with respect to the full Finite Element (FE) model. The deformable configuration for the interface generally showed the most accurate results, while the rigid configuration was the most efficient across the board. The beam configuration did not always follow an expected trend based on the order of elasticity values of the assigned materials. Based on the deformation results and the time associated with ROM generation and use-pass, multiple optimal solutions from the DoE are discussed.@en

The future of reliability is bright as each electronics company is spending 1–5% of their annual sales on cost of non-quality. These costs are related to product failures prior to the end of its warranty period. If even a portion of these costs are reduced, it would result in a substantial profit increase. Progress in the area of reliability can be found in five directions; (i) multi-scale and multi-physics simulations for physics of degradation; (ii) AI-based control systems in advanced production; (iii) smart sensoring and big data analysis; (iv) reliable materials and reliability testing; and (v) prognostics and health management/digital twin for condition monitoring. In this chapter, we discuss these directions and what it would mean for the future developments of the reliability domain.

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Silver sintering offers a promising landscape for Pb-free die attachment in electronics packaging. However, the sintered interface properties are highly process-dependent and deviate from bulk silver properties. Conventional measurement methods do not adequately capture the die-attach application geometry. Hence, this study introduces a novel methodology for characterizing thin bond-line interfaces with high-conductive materials. The transient heat flux impedance ΔZth(t, Δx) was measured between two thermally sensitive devices interconnected using pressureless Ag-sintering material. A correction factor was derived, based on thermal half-space principles, to account for non-uniform heat spreading over the die-attach interface. Experimental findings estimate an effective conductivity of ∼115W/mk for the pressureless Ag-sintered interface. The measurement results were validated by measuring a SAC305 soldered interface, which exhibited ∼55 W/mK, and a non-conductive epoxy interface of ∼2.5 W/mK. Voids on the die-attach layer, resulting from material processing, were identified to influence the interface thermal behavior. An uncertainty analysis was further discussed, emphasizing equipment tolerances, measurement sensitivity, and geometrical and thermal anisotropies. The article concludes with a comparative summary of the proposed methodology against conventional methods, highlighting differences in working principle, thickness range, measurement parameters, and their advantages and limitations.@en

Digital Twins (DT) play a key role in Industry 4.0 applications, and the technology is in the process of being mature. Since its conceptualisation, it has been heavily contextualised and often misinterpreted as being merely a virtual model. Thus, it is crucial to define it clearly and have a deeper understanding of its architecture, workflow, and implementation scales. This paper reviews the notion of a Digital Twin represented in the literature and analyses different kinds of descriptions, including several definitions and architectural models. A new fit-for-all definition is proposed which describes the underlying technology without being context-specific and also overcomes the pitfalls of the existing generalised definitions. In addition, the existing three-dimensional and five-dimensional models of the DT architecture and their characteristic features are analysed. A new simplified two-branched model of DT is introduced, which retains a clear separation between the real and virtual spaces and outlines the latter based on the two key modelling approaches. This model is then extended for condition monitoring of electronic components and systems, and a hybrid approach to Prognostics and Health Management (PHM) is further elaborated on. The proposed framework, enabled by the two-branched Digital Twin model, combines the physics-of-degradation and data-driven approaches and empowers the next generation of reliability assessment methods. Finally, the benefits, challenges, and outlook of the proposed approach are also discussed.@en

Electronic packages with solder interconnects, such as Chip Scale Packages (CSP) and Ball Grid Arrays (BGA), are extensively utilized in various applications, including cell phones, smartwatches, and electric vehicles. The advancements in technology and the features within these applications have led to an increase in power cycles within the packages. This combined with a reduced time to market makes their reliability testing more challenging. With the increased power cycles, even the small temperature variations (ΔT) within an Integrated Circuit (IC) package contribute to the increased susceptibility of devices to failures, often triggering a complex interplay of competing failure modes. Thus, it is crucial to understand the interplay between various failure mechanisms in real-world scenarios for evaluating and overseeing the dependability and efficiency of electronic systems. This paper presents an overview of the impact of small temperature variations on component reliability. In addition, a simulation-based preliminary study is carried out on a Wafer-Level Chip Scale Package (WLCSP) by implementing a thermal load corresponding to an active power cycle. The results are analyzed to locate possible failure locations within the solder bumps based on the accumulated plastic strains for different amplitudes of thermal load (ΔT). Finally, the necessity for a new testing strategy based on variable (ΔT) is highlighted.

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Resin-reinforced Ag sintering materials represent a promising solution for die-attach applications in high-power devices requiring enhanced reliability and heat dissipation. However, the presence of resin and intricate microstructure poses challenges to its thermal performance, and improvement strategies remain unclear. This work utilizes 3D FIB-SEM nanotomography to reconstruct the microstructure of this material under various process conditions. The analysis reveals that, even with an Ag volume fraction as low as 47.3%, Ag particles form a robust 3D network. Geometric tortuosity quantifies the effect of different sintering conditions on the Ag particle network in all spatial directions. Effective thermal conductivity is simulated based on realistic microstructure models. Results show a significant negative correlation between tortuosity and effective thermal conductivity. Increasing sintering temperature in Model B notably reduces tortuosity and enhances effective thermal conductivity. Sensitivity analysis underscores the dominant role of Ag volume fraction in regulating effective thermal conductivity. Finally, transient thermal impedance measurement of this material as a thin die-attach layer in actual high-power devices demonstrated its application potential. This article strives to explore the relationship between process, microstructure, and thermal properties of this material to provide a reference for further development.

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Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

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In this article, we provide a comprehensive review of defect formation at the atomic level in interfaces and gate oxides, focusing on two primary defect types: interface traps and oxide traps. We summarize the current theoretical models and experimental observations related to these intrinsic defects, as they critically impact device performance and reliability. By integrating theoretical insights with experimental data, this review provides a thorough understanding of the atomic-scale interactions that govern defect formation.

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