Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (?SM) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 µm technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of µWs.

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This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm2, achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 μW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoMSNDR of 182.7 dB.

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This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm2 in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

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This article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm ² and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 \mu \text{W}. This results in a Schreier figure of merit (FoM) of 183.6 dB.

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Class-D amplifiers are often used in high-power audio applications due to their high power efficiency. They typically employ pulse-width modulation (PWM) at a fixed carrier frequency, which may cause electromagnetic interference (EMI). Setting this frequency f_PWM) below the AM band (535 to 1605kHz) helps mitigate this, but its harmonics still contain substantial energy and must be filtered out by bulky LC filters with low cut-off frequencies (f_c = 20 to 40 kHz), significantly increasing system cost and size. Stability considerations also constrain the amplifier's unity-gain frequency to be < mathrm{f} {mathrm{PWM}}/pi [1], compromising the audio-band loop gain required to suppress output-stage nonlinearity. Setting f_PWM above the AM band helps increase f_c and allows a higher loop gain [2]. However, this results in narrower pulses at higher power levels (higher modulation index), which cannot be faithfully produced by the output stage, thus exacerbating its non-linearity. Delta-sigma modulation (DeltaSigma M) has fixed pulse widths and does not suffer from these narrow-pulse artefacts. However, the out-of-band noise of 1bit modulators then requires larger LC filters. Moreover, high-order loop filters must be used to achieve sufficient SQNR, which then require additional techniques to maintain stability as the modulation range approaches 100% [3].

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This paper presents a discrete-time (DT) zoom ADC for audio applications. A 2b quantizer in combination with a low power “fuzz” suppression technique, results in a significant improvement in linearity and energy-efficiency over previous designs. The ADC occupies 0.27mm 2 in 0.16μm CMOS and consumes 440μW from a 1.8V supply. In a 20kHz BW, it achieves 109.8dB DR and 106.5dB SNDR, resulting in a state-of-the-art Schreier FoM of 186.4dB.@en

This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ Σ M-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4- Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.

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This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 ×m CMOS process, occupies 0.27 m m² and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 ×W. This results in a state-of-the-art Schreier FoM of 183.6 dB.

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This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.@en

This paper presents a readout circuit for a carbon dioxide (COࠢ) sensor that measures the CO₂-dependent thermal time constant of a hot-wire transducer. The readout circuit periodically heats up the transducer and uses a phase-domain Δ Σ modulator to digitize the phase shift of the resulting temperature transients. A single resistive transducer is used both as a heater and as a temperature sensor, thus greatly simplifying its fabrication. To extract the transducer's resistance, and hence its temperature, in the presence of large heating currents, a pair of transducers is configured as a differentially driven bridge. The transducers and the readout circuit have been implemented in a standard 0.16μm CMOS technology, with an active area of 0.3 and 3.14 mm², respectively. The sensor consumes 6.8 mW from a 1.8-V supply, of which 6.3 mW is dissipated in the transducers. A resolution of 94-ppm CO₂ is achieved in a 1.8-s measurement time, which corresponds to an energy consumption of 12 mJ per measurement, >10x less than prior CO₂ sensors in CMOS technology.@en

The measurement of carbon-dioxide (CO2) concentration is very important in home and building automation, e.g. to control ventilation in energy-efficient buildings. This application requires compact, low-cost sensors that can measure CO₂ concentration with a resolution of <200 ppm over a 2500ppm range. Conventional optical (NDIR-based) CO₂ sensors require components that are CMOS-incompatible, difficult to miniaturize and power-hungry [1]. Due to their CMOS compatibility, thermal-conductivity-based sensors are an attractive alternative [2,3]. They exploit the fact that the thermal conductivity (TC) of CO₂ is lower than that of the other constituents of air, so that CO2 concentration can be indirectly measured via the heat loss of a hot wire to ambient. However, this approach requires the detection of very small changes in TC (0.25 ppm per ppm CO2 [3]).

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Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.

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This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &#x0394; &#x03A3; ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-&#x03BC;m CMOS process, the prototype occupies 0.26 mm&#x00B2; and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 &#x03BC;W. This results in a Schreier figure of merit (FoM) of 185.8 dB.

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This paper reports a readout circuit capable of accurately measuring not only the resistance of a resistive transducer, but also the power dissipated in it, which is a critical parameter in thermal flow sensors or thermal-conductivity sensors. A front-end circuit, integrated in a standard CMOS technology, sets the voltage drop across the transducer, and senses the resulting current via an on-chip reference resistor. The voltages across the transducer and the reference resistor are digitized by a time-multiplexed high-resolution analog-todigital converter (ADC) and post-processed to calculate resistance and power dissipation. To obtain accurate resistance and power readings, a voltage reference and a temperature-compensated reference resistor are required. An accurate voltage reference is constructed algorithmically, without relying on precision analog signal processing, by using the ADC to successively digitize the base-emitter voltages of an on-chip bipolar transistor biased at several different current levels, and then combining the results to obtain the equivalent of a precision curvature-corrected bandgap reference with a temperature coefficient of 18 ppm/°C, which is close to the state-of-the-art. We show that the same ADC readings can be used to determine die temperature, with an absolute inaccuracy of ±0.25 °C (5 samples, min-max) after a 1-point trim. This information is used to compensate for the temperature dependence of the on-chip polysilicon reference resistor, effectively providing a temperature-compensated resistance reference. With this approach, the resistance and power dissipation of a 100 Ω transducer have been measured with an inaccuracy of less than ±0.55 Ω and ±0.8%, respectively, from -40 °C to 125 °C.@en

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm² in the 0.16- μm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

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This paper reports a readout circuit for a resistive CO2 sensor, which operates by measuring the CO2-dependent thermal conductivity of air. A suspended hot-wire transducer, which acts both as a resistive heater and temperature sensor, exhibits a CO2-dependent heat loss to the surrounding air, allowing CO2 concentration to be derived from its temperature rise and power dissipation. The circuit employs a dual-mode incremental delta-sigma ADC to digitize these parameters relative to those of an identical, but isolated, reference transducer. This ratiometric approach results in a measurement that does not require precision voltage or power references. The readout circuit uses dynamically-swapped transducer pairs to cancel their baseline-resistance, so as to relax the required dynamic range of the ADC. In addition, dynamic element matching (DEM) is used to bias the transducer pairs at an accurate current ratio, making the measurement insensitive to the precise value of the bias current. The readout circuit has been implemented in a standard 0.16 μm CMOS technology. With commercial resistive micro-heaters, a CO2 sensing resolution of about 200 ppm (1σ) was achieved in a measurement time of 30 s. Similar results were obtained with CMOS-compatible tungsten-wire transducers, paving the way for fully-integrated CO2 sensors for air-quality monitoring.@en

Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ΔΣ ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ΔΣ conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.@en