Class-D audio amplifiers produce electromagnetic interference (EMI), which often needs to be suppressed by an external LC filter. However, due to component nonlinearity, this filter can itself cause significant distortion. This article presents a class-D amplifier that suppresses LC filter nonlinearity by 49 dB and is robust to ±30% variations in its cutoff frequency. This is achieved by a dual-loop architecture, in which an inner loop provides stability, while an outer loop provides the high gain needed to suppress the LC filter and output-stage nonlinearity. A prototype, implemented in a 180-nm BCD process, achieves -121.5-dB total harmonic distortion (THD) and -107.1-dB THD+N, which is maintained to within 3 dB even as the LC filter cutoff frequency is varied from 62 to 106 kHz. It can deliver a maximum of 21 W into a 4-Ω load with 87% efficiency and 12 W into an 8-Ω load with 91% efficiency, measured at 10% THD.

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Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in televisions, laptops, etc. Such speakers can be modelled as a large capacitive load, and so are typically driven by a Class-AB amplifier via a series resistor that ensures driver stability, and limits load current, but wastes power [1], [2]. In [3], the Class-AB amplifier is replaced by a more power-efficient Class-D amplifier (CDA) in series with an additional inductor. However, a series resistor is still required to damp the resulting LC resonant circuit, which could otherwise draw excessive currents when excited by large-signal distortion (e.g. clipping) harmonics around the LC resonance frequency. Alternatively, by using a feed-forward architecture based on LC filter diagnostics to limit overshoot currents, the series resistor can be replaced by a second inductor, at the expense of increased system complexity and cost [4].@en

Class-D amplifiers (CDAs) are often used in audio applications due to their superior power efficiency. Due to the sensitivity of the human ear, a large dynamic range (DR) is desired, and audio DACs with up to 130dB DR are commercially available [1]. However, the DR of the CDAs they drive is typically much lower [2]-[4], mainly due to the thermal noise introduced by the input resistors of their resistive feedback networks. Reducing this resistance is difficult, as it reduces the CDA's input impedance and increases the required loop-filter capacitance. Alternatively, the CDA could be configured as a capacitively coupled chopper amplifier (CCCA), whose capacitive feedback network could then achieve low noise without reducing input impedance. However, the large PWM component present at its output would then saturate its input stage. By exploiting the inherent PWM filtering present in a feedback-after-LC architecture, this paper presents a capacitively coupled chopper CDA, resulting in significantly improved DR and THD+N. The prototype achieves 8V_RMS of integrated output noise (A-weighted), a 121.4dB DR, and -1 09.8dB THD+N while delivering a maximum of 15/26W into an 8/4Omega load with 93%/88% efficiency.

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The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of -109.1 dB and can deliver a maximum of 14 W into an 8- \Omega load with 93% efficiency while occupying a silicon area of 5 mm2.

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This paper reports a chopper Class-D audio amplifier that obtains high PSRR over the entire audio band. A chopping scheme is proposed to minimize intermodulation distortion between pulse-width modulation (PWM) and chopping in the audio band. A high-voltage chopper is developed to handle a 14.4 V PWM signal. Timing matching techniques are proposed to minimize chopping nonidealities which ensure good PSRR and THD. Fabricated in a 180nm BCD process, the prototype obtains a PSRR >109 dB at 217 Hz and >83.7 dB over the entire audio band. It also achieves -109.1 dB/-98 dB THD/THD+N and can deliver a maximum of 13 W to an 8-Ω load.@en

This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of -107.8 dB/-102 dB and a peak efficiency of 91%/87% with 8- and 4-Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.

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