This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This article introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio, and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the tradeoffs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower power readout system with integrated cryogenic electronics.

Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary. However, QEC requires a large amount of data to be transferred from a cryogenic controller at 4 K to a classical processor at room temperature (RT). To bridge the gap, a high-speed data link between the quantum processor at CT and the classical counterpart at RT is needed. The proposed PAM4 TX architecture integrates a low-power 64:4 serializer structure, a high-speed 4:1 current-mode logic (CML) multiplexer, and a linear 6-bit digital-to-analog converter (DAC). Considering the challenges and benefits of CMOS operating at CTs, the TX architecture and circuitry are designed to exploit the maximum speed, while maintaining sufficient linearity. The fabricated 40-nm CMOS chip achieves a data rate of 40-Gb/s (36-Gb/s), an energy efficiency of 2.46 pJ/b (2.47 pJ/b), and 97.8% (96.6%) ratio of level mismatch (RLM) at CT (RT). While demonstrating an energy efficiency comparable to prior-art TXs in more advanced CMOS nodes at RT, the broad operating temperature of the proposed TX enables the required high-speed wireline link for large-scale quantum computers.

Continuous rounds of quantum error correction (QEC) are essential to achieve faulttolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits' decoherence time (<<T2∗~120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons' dispersive readout [3]. However, they have a few shortcomings. First, due to the temperatureindependent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2,3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TN by ~2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.

This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space- and quantum-computing applications.

Color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond, have demonstrated entanglement between remote (>1.3km) qubits and excellent coherence times [1], all while operating at a few Kelvins. Compared to other qubit technologies typically operating at mK temperatures, the higher operating temperature of NVs enables scalable 3D integration with cryo-CMOS control electronics [2], provides significantly more cooling power, and removes the interconnect bottleneck between the qubits and the electronics in prior art [3-5]. Yet, no cryo-CMOS controller for NV-based quantum computers (QC) has been demonstrated.

Quantum processors based on color centers in diamond are promising candidates for future large-scale quantum computers thanks to their flexible optical interface, (relatively) high operating temperature, and high-fidelity operation. Similar to other quantum-computing platforms, the electrical interface required to control and read out such qubits may limit both the performance of the whole system and its scalability. To address this challenge, this work analyzes the requirements of the electrical interface and investigates how to efficiently implement the electronic controller in a scalable architecture comprising a large number of identical unit cells. Among the different discussed functionalities, a specific focus is devoted to the generation of the static and dynamic magnetic fields driving the electron and nuclear spins, because of their major impact on fidelity and scalability. Following the derived requirements, different system architectures, such as a qubit frequency-multiplexing scheme, are considered to identify the most power efficient approach, especially in the presence of inhomogeneity of the qubit Larmor frequency across the processor. As a result, a non-frequency-multiplexed, 1-mm2 unit-cell architecture is proposed as the optimal solution, able to address up to one electron-spin qubit and 9 nuclear-spin qubits within a 3-mW average power consumption, thus establishing the baseline for the scalable electrical interface for future large-scale color-center quantum computers.

We realize high-fidelity gates for the two-qubit system formed by NV center. Using gate set tomography, we report gate fidelities exceeding 99%, and analyze the origin of the errors.

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-threshold-voltage (LVT) DRAM at 4.2 K is up to 2 × more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 ,000 × , thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil. T ^∗ ₂ coherence times up to 5.3μs and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.

Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures. As a result, traditional circuits, such as pass-gates, can operate down to 4.2 K, and their performance is augmented, e.g., digital circuits speeding up by 1.62× or lowering their energy per transition and energy-delay product by 4.24× and 2.33× , respectively. Unlike back biasing in FD-SOI, here all FBB voltages remain within the supplies, hence enabling on-chip and device-specific biasing. The proposed FBB technique thus represents a valuable design tool for bulk cryo-CMOS circuits.

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-and-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>38.7 dB (38.2 dB), SFDR<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB (<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB), and FOMW<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively.

State-of-the-art quantum computers already comprise hundreds of cryogenic quantum bits (qubits), and prototypes with over 10k qubits are currently being developed. Such large-scale systems require local cryogenic electronics for qubit control and readout, leaving the digital controllers for algorithm execution and quantum error correction (QEC) at room temperature due to the limited cryogenic cooling budget. The entire process, including qubit readout, data transmission, QEC, and algorithm execution, should be completed well within the qubit decoherence time, thus requiring a low-power high-speed communication link between the cryogenic quantum processor and classical processor located at room temperature. To this end, this paper presents the first cryo-CMOS high-speed 4-level pulse amplitude modulation (PAM4) wireline transmitter. Thanks to a power-efficient serializing architecture driving a 6-bit digital-to-analog converter (DAC), the 40-nm CMOS chip achieves a data rate of 40 Gb/s PAM4 with an efficiency of 2.46pJ/b and a ratio of level mismatch (RLM) of 97.8% at 4.2 K. While demonstrating an energy efficiency comparable to state-of-the-art transmitters in more advanced CMOS nodes, the extremely wide temperature operating range (4.2 K - 300 K) will enable future large-scale quantum computers.

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.

This article presents a wideband blocker tolerant receiver (RX) for fifth-generation (5G) user equipment applications. Two programmable zeros around the channel bandwidth are introduced to sufficiently suppress the close-in blockers of 5G applications. Since the effect of zeros gradually diminishes at larger out-of-band offset frequencies, an auxiliary current-sinking path is also introduced to reduce the RX input impedance at far-out offset frequencies. Moreover, a simple second-order transimpedance amplifier (TIA) is adopted to enhance the proposed RX selectivity. The utilized TIA synthesizes two complex conjugate poles to achieve a flat gain response and -40 dB/dec roll-off. A 40-nm CMOS RX prototype occupies 1.15mm2 and consumes 84-140mW from a 1.3-V supply voltage over the 0.5-3-GHz operating frequency range. The RX achieves a 160-MHz RF bandwidth, 2.6-4.2-dB noise figure, a -0.3-dBm blocker 1-dB compression point (B1dB), and an out-of-band third-order intercept point (IIP3) of 22.5 dBm. As a test case, using the 3GPP standard, a -15-dBm continuous wave (CW) close-in out-of-band blocker located at 85-MHz offset from the passband edges is applied to the RX. Thanks to the receiver's high selectivity, the RX achieves 100% throughput while detecting 100-MS/s quadrature phase shift keying (QPSK) signal with 16 dB higher power than the reference sensitivity.

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM textsubscript W) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.

By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters is adopted to attenuate close-in blockers by a -120 dB/dec roll-off. Finally, a translational feedback network is proposed to reduce the in-band gain ripple to below 0.5 dB and provide better than -19 dB input matching. Fabricated in the 40-nm CMOS technology, the proposed RX occupies a core area of 0.8 mm2 and consumes 108-176 mW from a 1.3 V supply over the RX's 0.5-3-GHz operating frequency. It achieves a 3-dB bandwidth of 150 MHz and a noise figure (NF) of 2.6-3.9 dB over the RX frequency range. Activating the parallel preselect filter degrades the NF by as little as 1.2 dB in the worst case. The RX shows a ≥q 97.5% throughput when receiving a 100-MS/s quadrature phase shift keying (QPSK) signal with 7.5-dB SNR and achieves a -9.7 dB error vector magnitude (EVM) while facing a -15 dBm continuous-wave (CW) blocker only 20 MHz away from the desired 100-MS/s QPSK signal with 12.3-dB SNR, thus satisfying the 3rd generation partnership project (3GPP) requirements with sufficient margin.