This thesis details the design of a high-speed RF delay locked loop(DLL). A new proposed phase detector architecture, coined the mixing phase detector, allows for phase detection at high frequencies, resulting in multiphase generation at these higher frequencies with a DLL. The mixing phase detector modulates the high frequency signal to DC, allowing for elementary circuits to be used that do not need high frequency capabilities. The mixing phase detector has been designed, entirely laid out, and will be taped out shortly, with which simulations have been performed and have been compared with the state-of-the-art. The simulated results, show the possibility of generating eight phases accurately at 11.1 GHz, which would be higher than the state-of-the-art.

Emerging, non-volatile memories are promising solutions to contemporary computing problems. These include In-Memory Computing, Neuromorphic Computing, and Machine Learning. We believe that these are not the only possible applications of non-volatile emerging memory devices and that these can be used effectively for tackling several challenges of the ”conventional” computer architecture. For instance, address decoders are an integral part of random access memories. They are typically implemented using fast logic optimised for low latency. They are, however, difficult to test, while their repair is considered to be impossible. In this thesis we research the possibility of a highly scalable and testable address decoder solution, based on Content-Addressable Memories build with ferroelectric transistors (FeFET). This solution can offer numerous advantages including transistor count close to state of the art designs, while outperforming them in terms of latency. In addition, a key advantage could emerge during the testing of this decoder; due to its regular 2D structure, it’s testability is comparable to that of conventional memory arrays. Moreover, it can enable higher production yields, considering that adding a few spare rows will enable end-of-production repair, in the presence of manufacturing defects. By additionally increasing the number of address bits stored in a single FeFET CAM cell, further potential area reductions of 30% - compared to the traditional dynamic NAND decoders - can be achieved.

This thesis focuses on the design and optimization of Successive-approximation (SAR) Analog-to-Digital Converter (ADC), with a primary focus on enhancing the Bit Error Rate (BER). SAR ADCs are widely used in various applications due to their power-efficient characteristics. The critical point addressed in this research is improving the BER of synchronous SAR ADCs without the necessity to reduce the sampling speed...

In this thesis for the Bachelor’s Degree in Electrical Engineering, a Control Unit (PCB and software) is designed for inside the UVC Seed Disinfection Machine of Team UVO. The machine consists of four modules: the Control Unit, the LED Driver, the motor controller and the power supply. The Control Unit allows a user to input the intensity per wavelength (for possible wavelengths: 255 nm, 275 nm, 285 nm and 395 nm), the exposure time and the motor speed.

The design of the machine, including all the modules, is aimed at achieving the optimal wavelength for inactivation and maximum and uniform irradiance, with the ability of changing radiation settings according to the desire of the user.

The Control Unit manages communication with the other modules, data storage, the User Interface, safety checks and system enabling. The thesis covers the design choices regarding the entire design, with an in-depth analysis of the hardware implemented safety checks, the graphical user interface and the design of the communication protocol.

Due to difficulties regarding uploading the code onto the PCB, not every developed functionality could be tested or implemented. However, the functionalities that were tested, did perform as expected. In addition to this, after the thesis has been submitted, more time will be spent on debugging the PCB, implementing and testing its features.

The objective for the graduation project of Team UVO is to provide a proof-of-concept of disinfecting cabbage seeds (Brassica oleracea capitata) from Alternaria using UVC LEDs. This thesis describes design process of the Control Unit module. The results of the decontamination process are provided in
Appendix F.

N-path filters promise to miniaturize RF receivers by replacing various fixed off-chip filters with a single programmable on-chip filter. This research investigates some of the issues of receivers with N-path filters under strong blocker conditions: reciprocal mixing and inherent nonlinearity. First, a technique for reciprocal mixing cancellation is explored and shown to be impossible using only mixers and baseband impedances. Second, the inherent nonlinearity of both bandpass and notch N-path filters are simulated and modelled. To validate this approach, a highly linear receiver is proposed and designed in 40nm CMOS. The receiver has a bandpass common gate architecture, with a notch filter in the feedback path, improving linearity. The filter is isolated using buffers, improving LO leakage. The common gate stage is IM3 compensated to obtain good
linearity (OOB IIP3 >20 dBm).

This report focuses on the design and implementation of both a detection system and an enclosure, which are designed to be used in a quantum random number generator. These parts are designed to be manufactured using off-the-shelf components to make the quantum random number generator affordable and accessible to a completely new user-group that cannot afford and operate the currently existing alternatives for quantum random number generation. After implementing the designed systems it is found that although the output of the system is random, true-randomness cannot be guaranteed using off the shelf components, because of the interference of classical noise sources.

In recent years, quantum computers have become increasingly popular, with high-profile companies in-vesting more and more resources into the development of quantum-computing prototypes. Such interest is motivated by the exponential increase in the computing power that quantum computers offer over classical computers, which may be used in several practical applications, such as producing faster and more accurate solutions to machine learning algorithms, the quantum simulations of molecules for drug and material synthesis, techniques that combat cybersecurity threats, and more. Quantum processors are typically placed in a dilution refrigerator, which cools down the processor to near absolute zero to make use of their quantum behavior. These fridges are large in scale and require multiple long wires from the processor to the readout/control equipment, which mostly resides at room temperature. However, although this approach is suitable for currently available systems with few quantum bits (qubits), it is unpractical for future quantum computers, with thousands or millions of qubits, due to the interconnect bottleneck. One solution isto move the readout/control circuits closer to the processor to avoid the need for bulky unreliable interconnects. However, this has proven to be difficult due to the limited cooling power of the fridges, which is below a few Watts at 4 K and below a few mW at temperatures below 100 mK. These limitations stress the need for low power readout/control circuitry of the processor as the number of qubits in a single processor increases. This thesis focuses on an ultra-low-power cryogenic amplifier design for the readout of spin qubits.Only recently, the cryogenic performance of Silicon-Germanium Heterojunction Bipolar Transistors (SiGe HBT) has been demonstrated to be specifically suited for the cryogenic readout of spin qubits, because of their ultra-low-power and their high sensitivity. This thesis focuses on the standard SiGe HBT available in the IHP 0.13μm SG13G2 BiCMOS process and on an optimized variant with modified doping profiles for enhanced current gain. As a first step, a comprehensive cryogenic (4 K or 15 K) DC characterization of the SiGe HBTs, CMOS transistors, and resistors is performed. This data proves the suitability of such technology for cryogenic application and will enable the future integration of a complete qubit readout, including SiGe front-end amplification and CMOS back-end post-processing. The measurement results of the SiGe HBT characterization show outstanding cryogenic performance for low power applications, with an attain-able current gain in the standard HBT of 100, 500, and 1000 at a power dissipation of 61nW, 2μW and 30μW,respectively, and, for the modified HBT, of 100, 500 and 1000 at a power dissipation of 5.5nW, 90nW, and140nW, respectively. To mimic the spin qubit readout, a discrete amplifier employing a SiGe HBT produced in the IHP SG13G2process has been built and used to characterize a single-electron transistor (SET), with both the SET and the amplifier operating at 4 K. By comparing the charge-stability diagram measured with room-temperature equipment, the proper operation of the proposed amplifier is demonstrated. Furthermore, the amplifier characterization showed a gain > 40 dB with an 113 kHz -3-dB bandwidth, and Signal-Noise Ratio (SNR)above 10 dB for a total measurement time of t<10μs, thus demonstrating performance compatible with the requirements for single-shot readout in state-of-the-art spin-qubit computers. Overall, the results show the capabilities of the SiGe HBT in low power cryogenic applications as well as the capabilities of the 0.13μmBiCMOS technology for the future full integration of qubit readout schemes.

Disruptive changes in the fields ofcryptography and quantum chemistry can be achieved through quantum computing,as specific computations can be sped up significantly. Thousands to millions ofqubits are required to perform these computations, illustrating the need forlarge quantum computers. These qubits must be cooled to cryogenic temperaturesin order to operate. Currently operations on few qubits can be done, these arecommonly controlled with room temperature equipment. However as the number ofqubits becomes larger, scalable and integrated electronics is required toreduce the interconnect. This has promoted research in cryogenic electronicsthat can be located close to the qubits. This thesis presents a low power,scalable cryogenic DC biasing solution for the biasing of spin qubits. Thepresented DC-DAC has been implemented in the Intel 22-nm finFET process. Unlikeconventional DACs, the designed DC-DAC periodically generates all possiblevoltages in the full scale output voltage range, and drives a multiplexer thatconnects a sample and hold capacitors when the right bias voltage for theelectrode has been generated. The DAC is able to achieve a high resolution of 16bits with low noise performance by using an offset-compensated switched capacitorintegrator. By offering a DC input to the integrator the full scale outputvoltage range can be generated, while using the offset-compensated switchedcapacitor integrator allows reduction of offset and 1/f noise which are expectedto degrade at cryogenic temperatures. The DC-DAC is designed to meet a largevoltage output range of 3 V, which breaks compliance with the nominal 1.8 Vcompliance of the thick oxide transistors in the process. While it is possibleto put larger voltages over the transistors, it is currently unknown how thiswill affect the reliability and behavior of the thick oxide transistors.Therefore, a two-stage amplifier has been implemented where the second stageuses a supply of 3.6 V. The voltage compliance in the second stage isguaranteed through cascode transistors that are dynamically biased byadditional DACs. As the addition of the second stage of the amplifier andcoarse DACs introduce another voltage domain, additional circuitry such aslogic level shifters, diode stacks and cascode transistors have been added toensure that voltage compliance is throughout the entire DAC. The DC-DACachieves a LSB step of 45.1휇푉,, avoltage output range of 3 푉,,integrated noise of 17 휇푉 rms and dissipates a total of 187휇푊, whilenot consuming more than 0.078 푚푚,2. Thehigh resolution, large voltage output range and low power of the DAC enableintegration of the DAC with the qubits, paving the way for scalable quantumcomputers.

This thesis presents two submodules which are part of 'an FM Chirp Waveform Generator and Detector for Radar', namely the mixer and the modulator. The goal of this project is to design and simulate these submodules from an educational perspective. The modulator is implemented as a single-ended common-base Colpitts oscillator with modulation capabilities added by means of varactor diodes. The carrier frequency of the presented modulator is tunable from 88 MHz to 108 MHz and the achieved modulation linearity for a sawtooth baseband signal is approximately 34 dB over the tuning range. The presented mixer consist of a double-balanced Gilbert-type topology with 29.5 dB (tunable) gain, 23 mW power consumption, high Input-Output isolation and single-ended output achieved by means of an active load. The project was carried out in the scope of the bachelor graduation project in the bachelor of electrical engineering at the Delft University of Technology.

The "FM Chirp Waveform Generator and Detector for Radar" is a Bachelor graduation project with an educational purpose. In this thesis, two modules of the whole system are designed and simulated. In particular, the sawtooth generator and the FM detector. The sawtooth generator is used to generate a linearly increasing signal, which can be used to make a chirp signal. The FM detector is used to extract the original information signal from the received FM signal. The used procedure consisted of determining possible implementations, setting up the design equations, choosing component values and simulating the circuits in ADS. The sawtooth generator was implemented using a ramp generator, Schmitt trigger and a voltage clamper while the FM detector was implemented using a balanced slope detector and a differential-to-single-ended converter. The results showed that the sawtooth generator can successfully produce a sawtooth waveform and that the FM detector can successfully retrieve it. It was concluded that both the modules satisfy all the requirements, meaning that they should work as expected in the whole system. Finally, the future steps were listed which, among others, include improving the linearity of the sawtooth generator and the FM detector.

This thesis introduces the concept of phase rotation cancellation (PRC) as a previously unknown error mechanism in narrow-band FSK systems, and proposes a new FSK demodulation algorithm to resolve PRC errors. Phase rotation cancellation is defined as an event where the signal phasor rotation in the IQ plane is temporarily cancelled by the rotation of quadrature noise. The PRC errors are the dominant error mechanism in narrow-band FSK due to the small dynamic range at the output of a conventional FSK demodulator. In addition, any pre-modulation filtering further reduces the dynamic range and increases the probability for PRC errors to occur. Based on the discovered characteristics of PRC errors, a novel FSK demodulation algorithm is developed that greatly improves detection accuracy in FSK systems. Furthermore, the novel demodulation algorithm allows for sub-datarate receiver bandwidth operation, which offers improved receiver sensitivity and blocker performance. It is shown that the new demodulation algorithm eliminates nearly all PRC errors, leaving only errors due to clicks. In a GFSK system with BT = 0.5 and h = 0.5, an improvement in receiver sensitivity of up to 4.4 dB is achieved with the new demodulation algorithm.

This work proposes a new charge pump design suitable for energy harvesting on small human wearable devices. By using only one system for both cold start and high efficiency harvesting, the required silicon area is heavily reduced. The most fitting energy transducer is determined to be a photovoltaic cell, based on aspects of voltage, power and size. Both indoor and outdoor lighting conditions are suitable. The literature on fully integrated voltage boosting with special attention to cold start shows that the capacitive charge pump is the best solution for high efficiency, low power and small size voltage boosting. For cold start applications, a Dickson charge pump with dynamic charge transfer switches is the best solution. For achieving high efficiency conversion, theMakowski charge pump is the best.
The proposed design combines the advantages of the Dickson charge pump for cold start and the high efficiency aspects of aMakowski charge pump for normal operation in one system with minimal silicon area. Using capacitor splitting, the conversion ratio of the cold start charge pump can be orthogonally chosen from
the conversion ratio of normal operation. Dynamic charge transfer switches are used for the cold start charge pump to increase the performance. An implementation of the proposed design is made in Cadence Virtuoso and is tested for cold start capability and efficiency across five process corners and three temperatures. The results prove that the proposed design can achieve high efficiency energy harvesting that is on average 5% below the efficiency of a normal Makowski charge pump. Cold start was achieved from 100mV that is boosted to a battery voltage of 1.8 V within the micro-watt power range. With these results, the proposed charge pump is suitable for photovoltaic energy harvesting in small devices. The required silicon area is reduced by 50%, compared to systems where cold start and high efficiency harvesting are provided by separate systems.
The proposed design is made into a lay-out, which is currently being tested and will be manufactured in the coming months.

Quantum computers are able to deal with large problems, like molecular modelling, financial prediction and cryptography. A classical controller is used to control the qubits of the quantum computer. A proposed controller, operating at 4K, needs a clean voltage supply in order to function well. The long interconnects between the room temperature power supplies and the 4K classical controller are not loss-less and do have parasitic capacitance and inductance. Low drop-out (LDO) voltage regulators are able to clean this dirty supply voltage and produce a stable, regulated voltage. Therefore, a cryogenic 40nm CMOS LDO voltage is designed. This regulated is designed with room temperature models and optimized for operating at 4K. The specification are competitive to other LDO voltage regulators.