A High-Speed Delay-Locked Loop for RF applications

Abstract

This thesis details the design of a high-speed RF delay locked loop(DLL). A new proposed phase detector architecture, coined the mixing phase detector, allows for phase detection at high frequencies, resulting in multiphase generation at these higher frequencies with a DLL. The mixing phase detector modulates the high frequency signal to DC, allowing for elementary circuits to be used that do not need high frequency capabilities. The mixing phase detector has been designed, entirely laid out, and will be taped out shortly, with which simulations have been performed and have been compared with the state-of-the-art. The simulated results, show the possibility of generating eight phases accurately at 11.1 GHz, which would be higher than the state-of-the-art.