This brief presents a linearization technique for open-loop amplifiers. It utilizes the exponential {V}{-}{I} transfer of MOS transistors in weak-inversion together with a weak form of resistive degeneration. By using a specific relationship between the input transconductance and the source degeneration resistance, the amplifier is shown to have a significant reduction ( \sim 50\times ) in its third-order distortion component. Based on this linearization principle, two amplifier topologies are proposed by implementing the degeneration in (a) pseudo-differential and (b) common-mode configuration. The pseudo-differential degeneration scheme allows the amplifier to achieve more than 80dB linearity for 150mV {\text {pp-diff}} input swing at the expense of 35% lower power-efficiency. The common-mode degeneration eliminates this power penalty but exhibits 10dB worse linearity. To ensure an optimal linearity over process variation, a foreground calibration scheme is used to detect the nonlinearity. The nonlinearity correction is done by adjusting the bias current of the amplifier. The proof-of-concept amplifiers are constructed on a stripboard to demonstrate the effectiveness of the proposed linearization technique. With an input signal of 50mV {\rm pp{-}diff} , the two topologies achieve-105dB and-95dB HD3, respectively, improving the linearity of the state-of-The-Art open-loop amplifiers by at least 30dB.

A 12-bit pipelined analog-to-digital converter (ADC) using a new integration-based open-loop residue amplifier topology is presented. The amplifier distortion is cancelled with the help of an analog linearization technique based on a tunable input-driven active degeneration. Amplifier gain and nonlinearity errors are detected in background using split-ADC calibration technique. The mismatch between the two half-ADCs is minimized by sharing the residue amplifier between the two half-ADCs and adding the calibration offset over time. Based on this "split-over-time" calibration architecture, a two-lane prototype ADC was fabricated in 28-nm CMOS that achieves 64-dB signal-to-noise + distortion ratio and 77dB spurious-free dynamic range at Nyquist input after calibration. Operating at 280 MS/s, the ADC consumes 13 mW from 1-V supply, exhibiting a Schreier figure-of-merit of 164.3 dB. By dissipating only 0.4 mW in the residue amplifiers, the linearization technique helps the ADC achieve an improvement of at least 3 dB in Schreier FoM over existing state-of-the-art ADCs with comparable architectures.

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV_pp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.