Improving Metastability in Synchronous SAR ADCs

Master thesis (2024)

Authors

J. Hildebrand Electrical Engineering, Mathematics and Computer Science

Contributors

K. Bult Electronics - EEMCS (mentor)
F. Sebastiano Quantum Circuit Architectures and Technology - EEMCS (mentor)
M. Babaie Electronics - EEMCS (graduation committee member)
Faculty
Electrical Engineering, Mathematics and Computer Science
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Published Date

21-08-2024

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

This thesis focuses on the design and optimization of Successive-approximation (SAR) Analog-to-Digital Converter (ADC), with a primary focus on enhancing the Bit Error Rate (BER). SAR ADCs are widely used in various applications due to their power-efficient characteristics. The critical point addressed in this research is improving the BER of synchronous SAR ADCs without the necessity to reduce the sampling speed...

Files

JH_thesis_final.pdf
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