An implementation strategy for high-power, high resolution, fully digital transmitters (DTX) is proposed. It is based on a high-speed CMOS controller featuring a high-density flip-chip interconnect to an LDMOS power MMIC containing large arrays of custom low-VT LDMOS gate segments configured in RF-power switch banks. Using a two-level thermometer approach and a novel symmetric control scheme for the activation of the gate segments, a high-resolution 11-bit DTX switch bank is realized. It can provide peak RF powers >10 W at 45/40% peak drain/system efficiency at 3.525 GHz.@en

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

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This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average P Out of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than -42/-40/-40/-38 dBc and an average error vector magnitude (EVM) of -36/-34/-34/-32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than -42/-41 (-43/-43) dBc and -34.6/-33.1 (-33.5/-33.9) dB, respectively.

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A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering radio frequency digital-to-analog converters (RFDACs) that feature an extra current division path to allow the generation of the optimum current-mode class-B drive profile for the final CG/CB PA, facilitating energy-efficient TX operation without compromising linearity. For this purpose, the DDRM uses signed-IQ mapping combined with a class-B harmonic rejection (HR) technique. In addition, an advanced dynamic biasing technique is introduced to further enhance the TX line-up efficiency in deep power back-off (PBO) region. The DDRM driver standalone can provide 19.6-dBm RF peak output power. It supports a '160-MHz 256-QAM' signal at 2.4 GHz with an adjacent channel leakage ratio (ACLR) of -40.3 dBc and an error vector magnitude (EVM) of -33 dB, without using any digital pre-distortion (DPD). When connected to a CB SiGe PA, the overall TX line-up achieves an output power of 27 dBm and an overall TX system efficiency of 20%. This DPD-free TX line-up achieves an ACLR of -37.7 dBc and an EVM of -30 dB, respectively, when operating with an '80-MHz 64-QAM' signal at 2.2 GHz.

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A high-power fully-digital Doherty transmitter (DDTX) is proposed. It features two segmented LDMOS output switch banks implemented in a custom V T -down-shifted LDMOS technology. A 40 nm CMOS controller digitally activates the individual LDMOS gate segments of the output stage at RF speed. An inverted Doherty power combiner is proposed that features non-short circuited 2 nd harmonic conditions for the main and peak switch banks to boost the RF bandwidth. To guarantee smooth output power and efficiency vs. frequency, a 2 nd harmonic trap is introduced in the power combiner, yielding an RF bandwidth of > 400 MHz. The realized demonstrator can achieve over 39 W peak output power. Its highest drain and system efficiencies, respectively 60 % and 57 %, were found at 34.2 W of output power, while in power back-off its peak drain and system efficiencies are 52 % and 48 % respectively. Over a 25 dB output range, the system efficiency is within 4 percent points of the drain efficiency.@en

In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks.@en

This article presents an efficient digital polar transmitter (DPTX) at mm-wave frequencies that exploit a novel N -way series Doherty combiner (SDC) to enhance its drain and system efficiency at deep power back-off (PBO). The proposed N -way SDC is scalable and can be implemented elegantly using N transformers and N-1 shunt capacitors. As a proof of concept, a four-way Doherty DPTX is realized with the proposed SDC in which four identical but independent digital phase modulators deliver a phase-modulated constant envelope signal to their corresponding digital power amplifiers to perform the required amplitude modulation. Fabricated in a 40nm CMOS process, the proposed DPTX occupies a core area of 1.1 mathrm {mm^{2}} and exhibits 18.7dBm saturated output power and <-40dBc LO feedthrough. It demonstrates a drain efficiency of 33%/36%/22% at 0/4.5/11.5dB PBO at a 29.5GHz carrier frequency. While transmitting a 300MHz 64-QAM OFDM signal with a peak-to-average power ratio of 10.7dB, the DPTX achieves 18%/8% average drain/system efficiency, -27.6dB error vector magnitude, and -27.5dBc adjacent channel leakage ratio. To the best of our knowledge, this work is the first reported mm-wave Doherty transmitter that includes the entire chain all the way from the binary data stream up to the modulated mm-wave output signal.

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To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(\phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $\rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $\text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $\mathrm{I}/\mathrm{Q}$ to $\rho/\phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $\mathrm{I}_{\text{MP}}=\mathrm{I}-\mathrm{Q}$, QMP $=\sqrt{2}\mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $\mathrm{I} /\mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.@en

This article presents a wideband 2× 12 -bit direct-digital RF modulator (DDRM) operating in a 0.5-to-3-GHz band for 5G transmitters. The proposed digital Cartesian modulator features an advanced IQ-mapping technique to boost RF power by 3 dB and suppress the I/Q image. To verify the proposed concept, a 40-nm CMOS prototype is implemented whose RF peak output power at 2 GHz is more than 14 dBm. It achieves an adjacent-channel leakage ratio (ACLR) of -52 dBc and an error vector magnitude (EVM) of -40 dB for a 20-MHz 256-QAM signal at 2.4 GHz. With a 320-MHz 256-QAM signal, the measured ACLR and EVM performances are better than -43 dBc and -32 dB at 2.4 GHz, respectively, without using any digital pre-distortion.

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Fully digital transmitters (DTXs) have the potential of replacing analog-intensive transmitter (TX) line-ups in future massive multiple-input and multiple-output (mMIMO) systems since they hold the promise of higher system integration level and energy efficiency. DTX operation so far has been limited to low RF output powers. This article introduces a concept that enables high-power DTX operation. A DTX demonstrator targeting both high output power and high efficiency is realized as a proof of concept. It is based on a custom <formula> <tex>${V_{T}}$</tex> </formula> -shifted laterally-diffused MOS (LDMOS) technology, which is utilized to implement a segmented high-power output stage operated in class-BE. A low-voltage high-speed 40-nm CMOS controller drives the individual output stage segments at gigahertz rates. Measurements show the promising results for the proposed high-power DTX concept and provide valuable lessons for future DTX implementations.

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A 40nm CMOS wideband digital Cartesian push-pull inverted Doherty operating in class-E is presented. Wideband Doherty operation is achieved over a 1.9-to-3GHz frequency band, using an off-chip power combining network. The fully digital transmitter (DTX) provides 25.3dBm peak power with a drain/DTX line-up efficiency (DE/SE) of 58.7%/44.9%, respectively, at 2.4GHz. When operated with a 160MHz 256-QAM OFDM signal, it achieves 46.1%/32.7% average DE/SE, with an ACLR and EVM better than −40.6dBc and −33.9dB, respectively, using a simple memory-less digital pre-distortion (DPD).@en

This letter presents a millimeter-wave (mm-wave) vector-modulated phase shifter (VMPS) for phased-array applications. To improve the phase-shift accuracy without drastically increasing design complexity, the proposed VMPS structure employs variable-gain amplifiers (VGAs) that offer 2× better resolution at their low-gain states compared to their high-gain states. A two-stage current-reused structure is also proposed to implement the desired VGAs with minimal layout complexity, negligible gain penalty, and no extra power. Moreover, the proposed VMPS can maintain its phase-shift accuracy even at lower voltage gains. Fabricated in 40-nm CMOS, the prototype core consumes 11 mW from a 1.1-V supply and occupies a core area of 0.19 mm2. At 28 GHz, with a phase resolution of 0.61°, the measured RMS phase error is 0.23° at the maximum gain and remains <0.5∘ at 9-dB gain back-off. With a fixed set of VGA’s codewords, the RMS phase error and gain variation error are, respectively, lower than 1° and 0.24-dB over a bandwidth of 23.8–30.4 GHz.

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This thesis focuses on digital-intensive up-converters for sub-6GHz wireless communication. Nowadays, wireless cellular communication is entering its 5th generation (5G), driven by the demand for faster mobile access and higher data throughput. 5G utilizes larger modulation bandwidths, higher-order modulations, and (many) more transmitters and receivers than its precessors, requiring higher system efficiency, flexibility, and integration of the transmitter (TX). An essential building block in the TX system is the RF modulator that converts the baseband data to an RF signal. New modulator architectures and circuits are required to handle the increased 5G modulation bandwidths linearly and energy-efficiently. Along with the progress in wireless communication, nano-scale CMOS technologies are advancing toward their physical limitations. Transistors have become smaller and more suited towards digital signal processing (DSP). Moreover, their high-frequency performance has improved, enabling RF analog/mixed-signal circuits. These improvements offer digital-intensive transmitters (DTXs) the opportunity to enter a territory that has been the traditional stronghold of analog-intensive TXs. Consequently, the research question of this dissertation is “What if we change the nature of the RF front-end, such that we can start truly benefiting from the power of CMOS in “digital” (switching) operations?” This thesis proposes new digital-intensive TX line-ups and up-converters architectures with enhanced linearity, bandwidth, and power efficiency to answer this question...@en

Fifth-generation (5G) mm-wave communication systems support high-order modulation schemes with large peak-to-average power ratios (PAPR). This demands transmitter (TX) operation in deep power back-off (PBO), thus degrading its average efficiency. Hence, several mm-wave Doherty PAs have been proposed [1], [3] to address this issue. However, the number of their peaking amplifiers (PAP) has been limited to two, mainly due to poor scalability, and high losses in the Doherty power combiner. Therefore, the efficiency enhancement was restricted to the 10dB PBO range. Furthermore, prior-art chiefly employed an analog class-AB amplifier for the main PA (PAM), degrading the system efficiency (SE) for two reasons. First, the conduction angle of an analog amplifier increases with a reduction of the drive signal amplitude, resulting in a Class-A-type efficiency roll-off that severely degrades the achievable PBO efficiency. Second, the output impedance of analog PAs is almost constant while the PAs' load significantly increases in PBO Doherty operation. This results in a load mismatch at PBO, degrading the PAs' gain and efficiency while giving rise to AM-AM and AM-PM distortion.

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An energy-efficient, intrinsically linear, digital class-C like operation-mode is investigated for use in high-power digital transmitters (DTXs), which target next generation mMIMO base stations that offer lower costs, higher integration, and improved system efficiency. The proposed operation utilizes class-B/C output matching in combination with duty-cycle reduction and current-mode operation of a segmented output stage. Its performance in terms of efficiency, output power, and linearity is benchmarked with analog class-B/C operation. The proposed digital class-C like operation has been experimentally verified using a fully-digital, dual TX line-up with VT-shifted segmented LDMOS output stages. All output stage segments are individually controlled by high-speed digital drivers implemented in 40 nm CMOS technology. The realized prototype provides 25.9 W (CW) output power with 75.7 % drain and 72.9 % system efficiencies, at 930 MHz and at 28 V drain supply.

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We present a wideband, 12-bit four-way Doherty Cartesian digital transmitter (DTX) featuring an innovative 50%-LO signed I/Q interleaved up-conversion technique that enables close to perfect orthogonal I/Q summation. The DTX incorporates a compact four-way lumped-element Doherty power combining network to enhance its average efficiency at deep power back-off (DPBO). It comprises a signed second-order hold (SOH) interpolation filter to suppress the sampling spectral replicas significantly. The proposed DTX is realized in a 40-nm bulk CMOS and delivers a peak output power of 27.54 dBm with drain and system efficiencies of 46.35% and 30.77%, respectively, at 5.3 GHz. At 12 dB DPBO, the realized DTX demonstrates a drain efficiency (DE) of 41.74%-39.27% in a 5.2-5.5 GHz band, respectively. Its intrinsic I/Q image, LO leakage, and C-IMD3/H 3BB for a 200 MHz tone spacing over a 4.8-6.2 GHz band are-64,-65, and-69 dBc, respectively, without calibration. Applying a simple memoryless 2× 1-D digital pre-distortion, its error vector magnitude and adjacent channel leakage ratio are lower than-31 dB and-39 dBc, respectively, for a six-carrier '40 MHz 256-QAM OFDM' signal with 18 dBm average output power and a 41% average DE. The signed SOH functionality is verified employing a four-carrier '80 MHz 512-QAM OFDM' signal with spectral purity of better than-35 dBc, while its baseband sampling frequency is 675 MHz.

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Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

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A high-power digital transmitter (DTX) concept, targeting future low-cost, highly-integrated and energy-efficient mMIMO base stations, is presented. The proposed approach bridges the 'historical' gap between low-voltage high-speed digital and high-voltage high-power RF devices. The resulting combination allows for a complete replacement of the traditional TX line-up, which includes signal-generation, up-conversion, and analog pre-drivers and power amplifier (PA), as such, facilitating drastic energy savings. The DTX principles are demonstrated by a dual TX line-up implemented in a dedicated VT-shifted LDMOS technology. Each 11-bit DTX line-up features 15 thermometer and 7 binary-weighted LDMOS output-stage segments, which are individually controlled by digital logic and high-speed drivers implemented in 40 nm CMOS technology. The realized DTX prototype exploits a 2.1 GHz centered class-BE output matching network and provides, at 20 V drain supply, 18.5 W (CW) output power with 66.7 % drain and 60.4 % system efficiencies. The suitability of the concept to handle modulated signals is demonstrated for a two-tone signal (Δf = 80 kHz), yielding an 1M3 < -51.4dBc and a 10MHz 256-QAM signal, achieving an ACLR of -46.1 dBc and 1.2 % EVM.

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This paper presents a wideband, 2× 12 -bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology. The proposed digital-intensive quadrature upconverter features an advanced I/Q-mapping unit cell to boost RF power, in-band linearity, and out-of-band spectral purity. The modulator provides more than 14 dBm RF peak output power. It achieves an ACLR of -52 dBc and an EVM of -40 dB when applying a 20 MHz 256 QAM signal at 2.4 GHz. When applying a 320 MHz 256 QAM signal at 2.4 GHz, the measured ACLR and EVM are better than -43 dBc and -32 dB, respectively, without applying any digital pre-distortion.

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We present a 1-3 GHz, 2×13-bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology as a driver for an external common-gate (CG) power amplifier (PA). The proposed digital-intensive quadrature up-converter features a pair of novel current-steering mixing DACs with an additional leakage path to boost the efficiency of the external CG PA. The realized DDRM also employs IQ-interleaving, harmonic rejection, and dynamic biasing to improve its spectral purity, in-band linearity, and system efficiency. The proposed digital up-converter prototype provides standalone more than 19.6 dBm RF peak output power. Without using any digital pre-distortion, it achieves an ACLR of-44.5 dBc and an EVM of-35 dB, when applying an 80 MHz 256 QAM signal at 2.4 GHz.

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