Fully digital transmitters (DTXs) have the potential of replacing analog-intensive transmitter (TX) line-ups in future massive multiple-input and multiple-output (mMIMO) systems since they hold the promise of higher system integration level and energy efficiency. DTX operation so far has been limited to low RF output powers. This article introduces a concept that enables high-power DTX operation. A DTX demonstrator targeting both high output power and high efficiency is realized as a proof of concept. It is based on a custom <formula> <tex>${V_{T}}$</tex> </formula> -shifted laterally-diffused MOS (LDMOS) technology, which is utilized to implement a segmented high-power output stage operated in class-BE. A low-voltage high-speed 40-nm CMOS controller drives the individual output stage segments at gigahertz rates. Measurements show the promising results for the proposed high-power DTX concept and provide valuable lessons for future DTX implementations.

Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

This article presents the first application of a digital-intensive intrinsically linear digitally controlled class-E technique in a Doherty configuration. By careful nonlinear segmentation and multiphase RF-clocking along with overdrive-voltage control and automatic duty-cycle correction, it is shown that even the nonlinearities related to Doherty operation can be fully handled by the underlying design such that digital predistorion (DPD) can be, in principle, omitted. The nonlinearity behavior of the whole digital Doherty power amplifier (PA) is analyzed, and closed-form equations are given to predict the AM-AM and AM-phase modulation (PM) curves. In addition, time/phase mismatch between the peak and main branches and the AM and PM signals is accurately compensated. In order to achieve the maximum intrinsic linearity, two separate chips with the same architecture, but different design parameters, are fabricated as the main and peak amplifiers in 40-nm bulk CMOS. To achieve a large RF bandwidth and high passive combiner efficiency, a differential low-loss, wideband Marchand balun-based Doherty power combiner, implemented using reentrant coupled lines with independent second-harmonic control is proposed, and together with the matching network is fabricated on a two-layer PCB. The measured peak/6-dB power backoff P OUT, drain efficiency/power-added efficiency at 2.4 GHz are 17.5 dBm/12.2 dBm, 57%/52% and 36%/25% with VDD main/peak = 0.6 V/0.7 V. Measured results without using DPD show -41-dBc adjacent channel power ratio (ACPR) and -36-dB error vector magnitude (EVM) for a 16-MHz OFDM signal at 2.5 GHz. By using DPD, the measured ACPR and EVM of a 16-MHz/32-MHz OFDM signals are -52 dBc/-48 dBc and -50 dB/-48 dB, respectively.

The maximum achievable linearity of a digital polar transmitter (DPTX) is mainly constrained by two RF-DAC associated nonidealities; namely, aliasing of sampling spectral replicas (SSR) of the AM and PM signals, and the presence of nonuniform quantization noise. In this work, using DPTX hardware linearization, in combination with PM SSR filtering and iterative learning control (ILC) algorithm improved by look-up tables (LUT), a CMOS DPTX is linearized close to its theoretical ACPR and EVM limits as predicted by its resolution. Using the ILC technique as underlying basis, an effective real-time direct-learning digital predistortion (DPD) technique is proposed. Measurement results show -60/-53 dBc ACPR and -60/-47 dB EVM using the ILC algorithm for 16/64 MHz OFDM signals, and -55/-48 dBc ACPR and -50/-44 dB EVM using the proposed DPD for 16/64 MHz OFDM signals. To the best of author's knowledge, this is the highest linearity reported for a DPTX operating with wideband signals.

A fully integrated RFDAC based phase modulator in 40nm bulk CMOS is presented. To boost in-band linearity and the frequency range of operation, a harmonic rejection RFDAC architecture that suppresses the 3^rd and 5^th harmonics is proposed. The achieved frequency agility of the phase modulator is verified over a 0.6-2.5GHz range yielding EVM of -34.5dB and -36dB for an 18Mb/s and 75Mb/s GMSK signals, respectively. The power consumption of the proposed phase modulator is 33 mW at 2.4GHz.

The CMS Hadron Calorimeter in the barrel, endcap and forward regions is fully commissioned. Cosmic ray data were taken with and without magnetic field at the surface hall and after installation in the experimental hall, hundred meters underground. Various measurements were also performed during the few days of beam in the LHC in September 2008. Calibration parameters were extracted, and the energy response of the HCAL determined from test beam data has been checked.