A Wideband Linear Direct Digital RF Modulator using Harmonic Rejection and I/Q-Interleaving RF DACs

Conference paper (2017)

Authors

Mohammadreza Mehrpoo External organisation
M. Hashemi Electronics - EEMCS
Y. Shen Electronics - EEMCS
T.G.R.M. van Leuken Signal Processing Systems - EEMCS
S.M. Alavi Electronics - EEMCS
L.C.N. de Vreede Electronics - EEMCS
Research Group
Electronics (EEMCS) (TU Delft)
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Published Date

2017

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2nd-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2×9-bit DDRM core occupies 0.21mm2 and consumes only 110mW at 1 GHz. Within the 0.9-3.1GHz frequency range, the peak output power reaches +9.2dBm and the 3rd/5th harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, -44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than -30 dB and -45 dB, respectively, and ACPR remains as low as -44 dBc up to a wide bandwidth of 110 MHz.

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