An implementation strategy for high-power, high resolution, fully digital transmitters (DTX) is proposed. It is based on a high-speed CMOS controller featuring a high-density flip-chip interconnect to an LDMOS power MMIC containing large arrays of custom low-VT LDMOS gate segments configured in RF-power switch banks. Using a two-level thermometer approach and a novel symmetric control scheme for the activation of the gate segments, a high-resolution 11-bit DTX switch bank is realized. It can provide peak RF powers >10 W at 45/40% peak drain/system efficiency at 3.525 GHz.@en

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

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Digital predistortion (DPD) enhances signal quality in wideband radio frequency (RF) power amplifiers (PAs). As signal bandwidths expand in modern radio systems, DPD's energy consumption increasingly impacts overall system efficiency. Deep neural networks (DNNs) offer promising advancements in DPD, yet their high complexity hinders their practical deployment. This article introduces open-source mixed-precision (MP) neural networks that employ quantized low-precision fixed-point parameters for energy-efficient DPD. This approach reduces computational complexity and memory footprint, thereby lowering power consumption without compromising linearization efficacy. Applied to a 160-MHz-BW 1024-QAM OFDM signal from a digital RF PA, MP-DPD gives no performance loss against 32-bit floating-point precision DPDs, while achieving -43.75 (L)/-45.27 (R) dBc in the adjacent channel power ratio (ACPR) and -38.72 dB in error vector magnitude (EVM). A 16-bit fixed-point-precision MP-DPD enables a 2.8× reduction in estimated inference power. The DPD code in PyTorch is publicly available on GitHub.

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A wideband harmonic rejection voltage-domain mixer using resistive scaling is presented with excellent linearity and high IF bandwidth. Thin-oxide devices with constant gate-to-source voltages (VGS) are utilized to maximize the switching linearity. A novel switching core topology providing low-impedance IF outputs is proposed to support wideband in-phase (I) and quadrature (Q) mixer outputs when loaded by ADCs. Eight LO clock phases, each with a 25 % duty cycle, are on-chip generated for quadrature down-conversion and harmonic rejection (HR). By cleverly activating and organizing the mixer branches, the RF mixer input impedance can be kept perfectly constant throughout all eight clock phases, enhancing the mixer’s linearity. The TSMC 40 nm-CMOS realized mixer reaches 20.9 dBm OIP3 at an IF of 50 MHz with a conversion loss of 22.5 dB. It offers an 800 MHz 3-dB IF bandwidth at a differential capacitive loading of 0.15 pF, with a total power consumption of 40.7 mW drawn from a 1.1 V supply. The mixer targets linear wideband base station observation receiver applications.@en

This paper presents an advanced yet simple digital pre-distortion (DPD) technique for digital I/Q transmitters (DTXs). Exploiting the I/Q orthogonality, an effective 2×1-D DPD procedure is proposed to bypass the exhaustive 2-D search of the entire constellation diagram. Utilizing this technique, a four-way Doherty DTX is linearized. Measurement results demonstrate that for a non-contiguous six-carrier OFDM-QAM signal with aggregated bandwidth of 150MHz, the ACPR is better than -47.3dBc, and EVM is better than -41/-40dB for channel-1/-6, respectively.

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The demand for faster mobile access and higher data throughput drives the evolution of wireless cellular communication, requiring larger modulation bandwidths and higher-order modulations and necessitating more efficient and flexible transmitter systems. Simultaneously, the advancements in nano-scale CMOS technologies have made transistors smaller and better suited for digital signal processing, with improved high-frequency performance for RF mixed-signal circuits. These advancements impact wireless RF transceivers creating the need to explore transmitter architectures beyond the level of the most established ones, which are exclusively analog up to date, by pushing them towards incorporating more digital circuitry. Consequently, the primary research question addressed in this is: “What are the potential performance advantages when the strength of (high-speed) digital CMOS is utilized within an RF front-end?” To answer this research question, this thesis proposes new architectures for digitalintensive transmitter line-ups. These architectures aim to enhance linearity, bandwidth, and power efficiency, and enable the full utilization of CMOS technology in digital operations within the RF front-end....@en

This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average P Out of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than -42/-40/-40/-38 dBc and an average error vector magnitude (EVM) of -36/-34/-34/-32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than -42/-41 (-43/-43) dBc and -34.6/-33.1 (-33.5/-33.9) dB, respectively.

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To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(\phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $\rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $\text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $\mathrm{I}/\mathrm{Q}$ to $\rho/\phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $\mathrm{I}_{\text{MP}}=\mathrm{I}-\mathrm{Q}$, QMP $=\sqrt{2}\mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $\mathrm{I} /\mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.@en

A 40nm CMOS wideband digital Cartesian push-pull inverted Doherty operating in class-E is presented. Wideband Doherty operation is achieved over a 1.9-to-3GHz frequency band, using an off-chip power combining network. The fully digital transmitter (DTX) provides 25.3dBm peak power with a drain/DTX line-up efficiency (DE/SE) of 58.7%/44.9%, respectively, at 2.4GHz. When operated with a 160MHz 256-QAM OFDM signal, it achieves 46.1%/32.7% average DE/SE, with an ACLR and EVM better than −40.6dBc and −33.9dB, respectively, using a simple memory-less digital pre-distortion (DPD).@en

Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

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We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C²MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10^-12 with a 60.9-ps eye width.@en

Line-of-sight millimeter-wave (mm-wave) 5G phased array systems are key solutions to overcome the free-space path loss while providing a multi-Gbit/s data throughput. To realize these systems, nanoscale CMOS technologies should be exploited to enable high integration, compact area, low cost, and high yield. Besides, 5G systems typically employ spectrally efficient complex modulation schemes with high peak-to-average power ratios (PAPRs), which demand the transmitter (TX) power amplifier (PA) to operate in power back-off (PBO), thus degrading its average efficiency. Many techniques such as outphasing [1,2], load-modulated balanced amplifiers (LMBAs) [3–4], and Doherty PAs (DPAs) [5–9] are adopted in mm-wave TXs to enhance efficiency at PBO. Among them, the Doherty is an “RF-in RF-out” PBO efficiency enhancement topology supporting signals with large modulation bandwidth. These mm-wave DPAs are inherently narrowband structures due to employing a lumped-element quarter-wave transmission line (QTL). Thus, the broadband operation is only feasible by increasing the complexity of the Doherty power combiner, compromising with its passive efficiency [7–8]. Also, in these architectures, their optimum PAE at PBO is still narrowband while providing broadband P1dB.@en

We present a wideband, 12-bit four-way Doherty Cartesian digital transmitter (DTX) featuring an innovative 50%-LO signed I/Q interleaved up-conversion technique that enables close to perfect orthogonal I/Q summation. The DTX incorporates a compact four-way lumped-element Doherty power combining network to enhance its average efficiency at deep power back-off (DPBO). It comprises a signed second-order hold (SOH) interpolation filter to suppress the sampling spectral replicas significantly. The proposed DTX is realized in a 40-nm bulk CMOS and delivers a peak output power of 27.54 dBm with drain and system efficiencies of 46.35% and 30.77%, respectively, at 5.3 GHz. At 12 dB DPBO, the realized DTX demonstrates a drain efficiency (DE) of 41.74%-39.27% in a 5.2-5.5 GHz band, respectively. Its intrinsic I/Q image, LO leakage, and C-IMD3/H 3BB for a 200 MHz tone spacing over a 4.8-6.2 GHz band are-64,-65, and-69 dBc, respectively, without calibration. Applying a simple memoryless 2× 1-D digital pre-distortion, its error vector magnitude and adjacent channel leakage ratio are lower than-31 dB and-39 dBc, respectively, for a six-carrier '40 MHz 256-QAM OFDM' signal with 18 dBm average output power and a 41% average DE. The signed SOH functionality is verified employing a four-carrier '80 MHz 512-QAM OFDM' signal with spectral purity of better than-35 dBc, while its baseband sampling frequency is 675 MHz.

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