Packaged integrated low-pass quasi-load insensitive (QLI) class-E matching is proposed for the realization of energy-efficient wideband Doherty and outphasing transmitters. In view of this, a dedicated QLI class-E harmonic matching technique, suitable for in-package integration has been developed, optimized, and evaluated. As proof of concept, very compact, as well as easy to assemble, dual-input load-modulating transmitters have been realized. In this paper, we focus on a QLI class-E matched wideband Doherty that provides 71% peak efficiency (± 3%) at 48-dBm saturated output power and 49% (± 7%) efficiency at 6-dB power backoff, over a 1200-MHz frequency span (1.4-2.6 GHz), yielding 60% fractional bandwidth (BW). When tested with single-carrier long-term evolution (LTE) signals, having a 7-dB peak-to-average ratio, average efficiency remains close to 49% (± 3%) for the entire 60% fractional BW. The realized demonstrator shows excellent linearizability with adjacent channel power ratio and normalized mean square error levels below -50 dBc and -36 dB, respectively, even when operated in simultaneous dual-band LTE operation.

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This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.@en

To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1-6]. DPAs are normally designed in a switched mode (Classes E/D/D-1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1-3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.@en

Doherty and Mixed-mode outphasing RF power amplifiers (PAs) that make use of package integrated quasi-load insensitive (Pi-QLI) Class-E GaN transistors are presented. The package integrated harmonic terminations facilitate very simple and compact amplifier implementations. Using these proposed devices, a “Class-E” Doherty PA with 58.3% average efficiency and -49 dBc ACPR after linearization, as well as, a Mixed-mode “Class-E” outphasing PA with an average efficiency of 66.6% and -51.6 dBc ACPR, after linearization using a single carrier WCDMA, PAR=7dB at 2.14GHz, are presented.@en

This paper presents a novel dual-input Doherty-Outphasing Power Amplifier (DOPA) architecture that combines the efficiency advantages of Doherty and Outphasing amplifiers in power back-off (PBO). The proposed architecture, utilizes Doherty operation from peak power to -6dB PBO and mixed-mode outphasing from -6 to -14 dB PBO. A 2.14 GHz 112W GaN DOPA has been designed to demonstrate the concept, it provides 66% peak efficiency and more than 50% efficiency over a 12 dB PBO range.@en