Body Channel Communication (BCC) utilizes the body surface as a low-loss signal transmission medium, reducing the power consumption of wireless wearable devices. However, the effective communication range on the human body is limited in the state-of-the-art BCC transceivers, where the signal loss between the body surface and the BCC receiver remains one of the main bottlenecks. To reduce the interface loss, a high input impedance is desired by the BCC receiver, but the DC-biasing circuits decrease the input impedance. In this work, a dynamically-sampling IFE is proposed to eliminate the DC voltage bias, resulting in a 90kΩ; high input impedance and a 94dB RF—IF conversion gain to reduce the interface loss in long-range BCC applications. The BCC transceiver chip is fabricated in 55nm CMOS process, taking a die area of 0.123mm². Measured results show that the chip extends the BCC range to 2m for both the forward and backward paths, where the transmitter and receiver consume 711μW power in total.

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The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term monitoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing technique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286 Omega and 162 fF, respectively. The power consumption and die area are reduced to 0.74 mu text{W} /Channel and 0.038 mm2/Channel, respectively.

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In this article, we propose a reconfigurable regulating rectifier with a wide operational range for wireless power transfer. The proposed three-mode rectifier achieves a broad range voltage regulation without global loop control to minimize the chip area occupation. Compared with previous work, more working modes and greater voltage gain allow the proposed rectifier to regulate lower input power, which extends the voltage regulation range. A local loop control scheme is proposed for voltage rectification with three modes. It adaptively senses the duty cycle of the mode signal to determine the working mode of the rectifier, and configure the rectifier to the desired mode for voltage regulation. The proposed system was designed and fabricated in a 180-nm BCD technology with an active area of 1.17 mm2. The measurement results show that the proposed system can rectify wide-range input ac power to a regulated output. The achieved voltage conversion ratiois between 0.95X and 2.68X, with a peak power conversion efficiencyat 87.4%.

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Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) dc-dc converters, based on several basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multiple VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This article presents a new recursive dc-dc converter system, which can dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in the conventional designs can be reused in this new architecture for increasing the load-driving capacity, power density, and power efficiency. To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of \text{0.71}\,\text{mA} and achieves a peak power efficiency of 93.1% with 105.3\,\mu \text{A/mm} {2} chip power density from a 2-V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236×, and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4, and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.

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This brief presents a 48V-to-1V 10-level dual inductor hybrid converter (DIHC) containing 11 on-chip switches and an off-chip gallium nitride (GaN) switch. Thanks to the 10-level Dickson switched-capacitor (SC) circuit, most of the voltage stress will be taken over by off-chip capacitors, which reduces the voltage stress of each switch to 4.8 V and takes full advantage of the voltage pressure on the 5-V on-chip transistors. This proposed structure is implemented in a 0.18- $\mu \text{m}$ BCD process to convert 48-V input to 1-V output with up to 18-A current load. The post-layout simulations show that a peak power efficiency of 90.6% can be achieved at 5.2-A loading and the power density is about 0.333 $W/mm^{2}$ considering the power stage area.

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The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the 2nd-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show -92 dBc/Hz@10 kHz phase noise and 6.8 μ W power.

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Body Channel Communication (BCC) offers a low-loss signal transmission medium for ultra-low-power wearable devices on human body [1]. However, the effective communication range on human body is limited to less than 1m in the state-of-the-art BCC transceivers [2], where the signal loss at the interface of body surface and BCC receiver remains to be one of the main bottlenecks. The limited communication range has blocked the popularization in many WBAN applications, such as signal transmission from to an intelligent insole to smart watch [3]. Relative to the high impedance of human body [4], the lower input impedance of BCC receiver induces significant signal loss. To reduce the interface loss, conventional interface front end (IFE) of BCC receivers was designed to be with a high input impedance [5], but the DC voltage bias decreased both the input impedance and signal gain of IFE.@en