Jiajie Fan
20 records found
1
During the operation of an LED array, its thermal and optical performances are always not equal to the superposition of the individual LED's characteristics because of a significant thermal coupling effect between the arrays. Based on this, this paper proposes an electrical–photo-thermal model, with considering both junction temperature and luminous flux, to predict the both the thermal and optical performances of LED arrays operated under different currents, case temperatures, and lighting methods. The junction temperature and luminous flux of a single LED operating under different driving currents and case temperature conditions are firstly collected to establish the luminous flux response surface model of a single chip. Then it is used to predict the luminous flux of an array, whose junction temperature is predicted using both thermal coupling matrix (TCM) and numerical models. Experiments verify the luminous flux of the LED array under different operation conditions and show that the proposed electrical–photo-thermal modeling can be used to predict the thermal and optical parameters of LED arrays with 95 % accuracy. Thus, it is effective for the fast prediction of the junction temperature and luminous flux of large LED systems with array structures, i.e. intelligent automotive lightings and displays.
@enDynamic mechanical analysis of (Ca,Sr)AlSiN3
Eu2+ phosphor/silicone composites aged under the temperature–humidity–sulfur coupled condition
Ultraviolet light-emitting diodes (UV LEDs) play an important role in inactivating novel coronavirus pneumonia, but the lack of rapid lifetime prediction can easily cause untimely failure detection, long product development cycles, and high costs. This study predicts the lifetime of UV LEDs based on the long short-term memory (LSTM) recurrent neural network (RNN). First, the equipment setup was designed to conduct an aging test to obtain a predicted length of life for the UV LED samples using a Weibull distribution. Next, LSTM RNN was employed to predict the lifetime of the UV LEDs based on the radiation power degradation. The results were then compared with those from nonlinear least squares (NLS) regression recommended by the IESNA TM-21 industry standard. Finally, the robustness of the two methods was analyzed by changing the starting times of the predictions. The results showed that the LSTM RNN proposed in this letter reveals not only a 29.7% lower lifetime prediction error compared with the NLS regression, but also a more stable robustness. Thus, the LSTM RNN method is found to be more accurate and more robust in predicting the lifetime of UV LEDs.
@enModern power electronics has the increased demands in current density and high-temperature reliability. However, these performance factors are limited due to the die attach materials used to affix power dies microchips to electric circuitry. Although several die attach materials and methods exist, nanosilver sintering technology has received much attention in attaching power dies due to its superior high-temperature reliability. This paper investigated the sintering properties of nanosilver film in double-side sintered power packages. X-ray diffraction results revealed that the size of nanosilver particles increased after pressure-free sintering. Compared with the pressure-free sintered nanosilver particles, the 5-MPa sintered particles showed a higher density. When increasing sintering pressure from 5 to 30 MPa, the shear strength of the sintered package increased from 8.71 to 86.26 MPa. When sintering at pressures below 20 MPa, the fracture areas are mainly located between the sintered Ag layer and the surface metallization layer on the fast recovery diode (FRD) die. The fracture occurs through the FRD die and the metallization layer on the bottom molybdenum substrate when sintering at 30 MPa.
@enWith the popularity and widespread application of high-power light-emitting diode (LED) in lighting industry, its reliability has gradually become one of research focuses.The failure of gold bonding wires in the traditional LED package has been a critical bottleneck that restricts its reliability. In this paper, the failure mechanism of LED under cyclically electrical loading is firstly identified through both gold bonding wire mechanical simulation and power cycling test experiment, which is the fatigue fracture of gold bonding wire. Then, two lifetime prediction methods, the acceleration factor extraction method based on current acceleration model and the strain-based Coffin-Manson analytical method, are established and verified with experimental results. The results show that the lifetime prediction accuracy of the proposed methods is high and they can achieve a fast and accurate reliability assessment for high-power LEDs with wire-bonding packaging technology.
@enDue to low power consumption, long lifetime and many other advantages, Light-emitting Diode (LED) has increased dramatically all over the world. Chip Scale Package (CSP) LED is a new LED package with small size, high current, and high reliability. For the CSP LED with smaller size and lower thermal resistance, phosphors and silicone are usually combined as the phosphors/silicone composite and prepared by using a high temperature cure process. However, for those CSPs which are not sufficiently cured, their reliability under a harsh environment (e.g. high temperatures and high humidity) will obviously decrease. In this study, the influence of temperature and ultraviolet light on the cure process of phosphor/silicone composites is studied and an optimal cure process is extracted accordingly. According to the cure experiment under different conditions, the results show that ultraviolet light and phosphor can promote the cure reaction of silicone. With the increase of ultraviolet light intensity and phosphor mass fraction, the cure rate of the silicone and phosphor/silicone composite is greatly increased as well.
@enAs one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.
@enHigh-power light-emitting diode (LED) chip-scale packages (CSPs) prepared by the flip-chip technology have become one of the most promising light sources. The die attach solder layer always plays an important role in heat dissipation, mechanical support, and electronic conductivity. Among different types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy shows its great competitiveness on solderability and mechanical properties for the interconnection of high-power LED CSPs. However, reliability problems caused by voids in the SAC305 solder limit its wide application in the high-power LED chip-scale packaging process. Existence of the voids has been considered as one of the major issues causing chip-on-substrate level reliability problems in microelectronic and optoelectronic devices. In this paper, mechanical and thermal properties of SAC305 solder layers with arbitrary voids used in high-power LED CSPs are studied with both finite-element simulations and experiments. The results show that void size and void position within the solder layer are the two most critical issues on the shear strength of interconnection and the chip-on-substrate level thermal distribution in high-power LED CSPs.
@enIn this paper, an integrated LED lamp with an electrolytic capacitor-free driver is considered to study the coupling effects of both LED and driver's degradations on lamp's lifetime. An electrolytic capacitor-less buck-boost driver is used. The physics of failure (PoF) based electronic thermal simulation is carried out to simulate the lamp's lifetime in three different scenarios: Scenario 1 considers LED degradation only, Scenario 2 considers the driver degradation only, and Scenario 3 considers both degradations from LED and driver simultaneously. When these two degradations are both considered, the lamp's lifetime is reduced by about 22% compared to the initial target of 25,000 h. The results of Scenario 1 and 3 are close to each other. Scenario 2 gives erroneous results in terms of luminous flux as the LED's degradation over time is not taken into consideration. This implies that LED's degradation must be taken into considerations when LED and driver's lifetimes are comparable.
@enOverdriving reliability of chip scale packaged LEDs
Quantitatively analyzing the impact of component
The spectral power distribution (SPD) is considered as the figureprint of a light emitting diode (LED). Based on the analysis on its SPD, a method to predict both lumen depreciation and color shift for the phosphor converted white LEDs (pc-LEDs) is proposed in this paper. First, the entire SPD of a pc-LED is predicted by superimposing two asymmetric double sigmoidal (Asym2sig) models, which represent the decomposed blue light and phosphor converted light peaks, respectively. For a better understanding of how the SPD model affects the photometric and colorimetric characteristics of a pc-LED, a sensitivity study of the SPD parameters is then performed on its luminous flux Φ, color coordinates CIE1976( u′, v′). Second, the evolutionary process of the SPD is predicted for a pc-LED with the color temperature as 3000 K under degradation testing. And based on these predicted SPDs, the drift curves of Φ, u′, v′, and du′ v′are further predicted. Finally, lifetimes of the pc-LED due to lumen depreciation and color shift are estimated simultaneously from the predicted Φ and du′ v′ drift curves.
@enLinear function fitting demonstrates a good linear relationship between color shift (Δu′ Δv′) and aging time almost for all the aging conditions. We can extrapolate the color shift Δu′ and Δv′ based on the fitted regression equations and then make the prediction for the total color shift Δu′v′.
Current stress can induce a different failure mode. Peak intensity reduction analysis reveals that the current stress accelerates the degradation of LED die.
Humidity test induced a substantial color shift both in u′ and v′. The u′ has an increased degradation rate after aging of 3000 h at 85%RH & 85 °C, there should be different degradation mechanisms during the whole humidity test. The molecular structure decomposition of silicone plates and then follows the silicone carbonization due to the long-term (3000 h) accumulated high localized temperature aging.@en
In this study, an electro-optical simulation method is developed to predict the light intensity distribution and luminous flux of an in-house fabricated GaN based blue LED chip. The entire modeling process links an electrical simulation with ANSYS and optical simulation with LightTools, by assuming a proportional relation between the distributed current density and light emission energy on the multiple quantum well (MQW) layer. Experimental results show that the proposed simulation method can give a good prediction on the light intensity distribution for a semi-packaged GaN based blue LED chip. Further analysis on the simulation results reveals that an increase of at most 8% of the luminous flux can be achieved when the current density is controlled to evenly distribute on the MQW layer whereas the chip structure and electro pattern remains the same.
@en