Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace’s equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments.@en

Double-sided packages for heat dissipation are an efficient thermal management mechanism for power semiconductor devices. A fan-out panel-level packaging (FOPLP), as one of the double-sided forms, exhibits excellent electro–thermal characteristics and provides low stray inductance and thermal resistance. Besides, the temperature at each point within the structure is closely related to its thermo–mechanical properties and device reliability. However, thermal resistance is limited in describing the temperature distribution. Finite element analysis (FEA) requires time-consuming construction of 3D models. Therefore, to depict the temperature distribution of FOPLP rapidly and accurately, a numerical heat transfer model was proposed for the double-sided package structure. The solution was obtained from the steady-state thermal balance Laplace equation using the separation of variables method. Several boundaries were analyzed to determine the specific parameters in the model. Finally, the temperature field predicted by the derived numerical model was compared with finite element simulation results. The proposed model was consistent with both Silicon (Si) and Silicon Carbide (SiC) FOPLP structures within the error of 15 % at the center of the device, which verified the validity and accuracy of the numerical model for double-sided heat dissipation. The proposed models and results could contribute to the development of effective thermal design tools for double-sided thermal power modules.

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SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of $8\times {8} \times {0}.{75}$ mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain-source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 °C/W; and 3) after 2000 thermal cycling cycles, drain-source ON-state resistance [RDS(on)] increased by less than 2%, which revealed the higher reliability of the package under thermal cycling.

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Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). To achieve superior reliability of packaging, we applied the nondominated sorting genetic algorithm with elitist strategy (NSGA-II) and ant colony optimization-backpropagation neural network (ACO-BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermomechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO-BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability aging tests on the prepared devices.

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Substrate metallization is a crucial factor affecting the mechanical properties of sintered nanoparticles in microelectronics applications, as it is essential for ensuring good adhesion between the substrate and the sintered material. In this study, we investigated the influence of metallization on pressure-assisted nanocopper sintering and analyzed the related mechanism of interaction using experiments and molecular dynamics simulation. In the first session, we bonded dummy dies on various substrates, including bare Cu, and substrates with Ag or Au metallization by nanocopper pressure-assisted sintering. The mechanical properties of the bonding layers were estimated using shear strength and SEM image analysis of fracture and cross-section morphologies under different sintering conditions. We found that the group of Cu-bare Cu have better bonding strength as the sintering temperature or assisted pressure is not high enough. However, as more energy input to the bonding layer, such as higher temperature or larger sintering pressure, the mechanical performance showed a significant increase. In the second session, a sintering model, which contained a single nanoparticle and substrate, was built to illustrate the effects of metallization from the perspective of solid-state wetting. The contact angle was estimated using a creative method, and the crystallization structure evolutions under different sintering conditions were analyzed. We found that the lattice boundary generated as the Cu nanoparticle coalescence with Ag or Au substrate, which may decrease the bonding strength. However, for Ag and Au metallization, limited interface diffusion can be observed at the neck region, where a few numbers of substrate atoms transmitted toward Cu nanoparticle, and the contact area was larger than that of bare Cu substrate. Finally, a simple uniaxial stretching simulation was conducted to prove the results of sintering simulation. This study provides valuable insights into the effects of metallization on pressure-assisted nanocopper sintering, which can contribute to the optimization of mechanical properties of sintered nanoparticles in microelectronics applications.@en

On the basis of the development and application requirements of flexible DC transmission techniques, a 1 kA/10 kV half-bridge IGBT press-pack module is studied. The module is composed of three subunits in series, and each subunit consists of IGBT chips in parallel. In order to solve the problem of chips failure caused by non-uniform rigid-contacting pressure in the press-pack modules, the elastic-contacting structure is designed to ensure excellent electrical connection between chips and contact terminal. During the operating conditions, the heat generated by IGBT chips can induce the increasing of internal temperature of the module, affecting the reliability of the module. A cooling structure is introduced between the subunits to solve the heat dissipation problem of the module. In addition, the thermal analysis of subunit and the cooling structure is performed by using the finite element simulation, and the chip layout and water-cooling scheme are optimized. The testing of electrical parameters of the IGBT module is also conducted.@en

For the relevant properties of pristine and doped (Si, P, Se, Te, As) monolayer WS₂ before and after the adsorption of CO, CO₂, N₂, NO, NO₂ and O₂, density functional theory (DFT) calculations are made. Calculation results reveal that the monolayer WS₂ doped with P and As atoms can be substrate materials for NO and NO₂ gas sensors. However, after the subsequent CDD and ELF calculations, it is found that P-doped monolayer WS₂ adsorbs NO and NO₂ in a chemical way, while As-doped monolayer WS₂ adsorbs NO and NO₂ in a physical way. Also, the charge transfer between As-doped monolayer WS₂ and NO is relatively small and not easily detected. Besides, As-doped monolayer WS₂ system exhibits greater differences in optical properties (the imaginary part of reflectivity and dielectric function) before and after the adsorption of NO₂ gas than before and after adsorption of NO gas. These differences in optical properties assist sensor devices in making gas adsorption-related judgments. Through the analysis of the recovery time, DOS and PDOS, As-doped monolayer WS₂ is also verified to be a promising NO₂ sensing material, whose recovery time is calculated to be as short as 0.169 ms at 300 K.

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Knowledge base question answering (KBQA) aims to answer a question over a knowledge base (KB). Early studies mainly focused on answering simple questions over KBs and achieved great success. However, their performances on complex questions are still far from satisfactory. Therefore, in recent years, researchers propose a large number of novel methods, which looked into the challenges of answering complex questions. In this survey, we review recent advances in KBQA with the focus on solving complex questions, which usually contain multiple subjects, express compound relations, or involve numerical operations. In detail, we begin with introducing the complex KBQA task and relevant background. Then, we present two mainstream categories of methods for complex KBQA, namely semantic parsing-based (SP-based) methods and information retrieval-based (IR-based) methods. Specifically, we illustrate their procedures with flow designs and discuss their difference and similarity. Next, we summarize the challenges that these two categories of methods encounter when answering complex questions, and explicate advanced solutions as well as techniques used in existing work. After that, we discuss the potential impact of pre-trained language models (PLMs) on complex KBQA. To help readers catch up with SOTA methods, we also provide a comprehensive evaluation and resource about complex KBQA task. Finally, we conclude and discuss several promising directions related to complex KBQA for future research.

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Cu-Ag core-shell (CS) nanoparticle (NP) is considered as a cost-effective alternative material to nano silver sintering material in die attachment application. To further reduce the cost, the thickness of the Ag shell can be adjusted. Whereas the shell thickness will also affect the thermal stability of the Cu-Ag CSNPs. In this study, molecular dynamics simulation was applied to study the thickness effect on the thermal behavior of Cu-Ag CSNPs. The melting points of CSNPs and Pure NPs can be determined by the evolutions of Potential Energy (PE), and the Lindemann index (LI) of the system. The results indicated that the melting points of CS NPs were lower than monometallic NP and the melting point of CS NP is influenced by the size of the Cu core and the number of lattice mismatches. Moreover, the distribution of atoms’ LI showed that the premelting point is independent of shell thickness. However, the fraction of atoms that occurred premelting is increased with the decrease of the shell thickness. Otherwise, we also simulated the sintering process of double CS NPs with equal size.@en

High electric-field stress is an effective solution to the recovery of irradiated devices. In this paper, the dependence of the recovery level on the magnitude of gate voltage and duration is investigated. Compared with the scheme of high gate-bias voltage with a short stress time, the transfer characteristics are significantly recovered by applying a low electric field with a long duration. When the electric field and stress time are up to a certain value, the threshold voltage almost approaches the limitation, which is less than that before irradiation. Meanwhile, the effect of temperature on the recovery of the irradiated devices is also demonstrated. The result indicates that a high temperature of 175 °C used for the irradiated devices’ annealing does not play a role in promoting the recovery of transfer characteristics. In addition, to obtain a deep-level understanding of threshold degradation, the first-principles calculations of three Si/SiO2 interfaces are performed. It is found that new electronic states can be clearly observed in the conduction bans and valence bands after the Si-H/-OH bonds are broken by electron irradiation. However, their distribution depends on the selection of the passivation scheme. Ultimately, it can be observed that the threshold voltage linearly decreases with the increase in interface charge density. These results can provide helpful guidance in the deep interpretation of threshold degradation and the recovery of the irradiated super-junction devices. @en

A fan-out panel-level packaging (FOPLP) with an embedded redistribution layer (RDL) via interconnection reduces the size, thermal resistance, and parasitic inductance of power module packaging. In this study, the effect of the RDL via size on the reliability of a FOPLP SiC MOSFET power module was investigated. To improve the thermal management and thermal cycling reliability of the designed SiC module, genetic algorithm (GA)–assisted optimization methods were proposed to optimize the RDL via size. First, the heat dissipation and the plastic work density of the SiC MOSFET module with various via diameters and depths were simulated using finite element simulations. Next, both the ant colony optimization-backpropagation neural network (ACOBPNN) with finite element simulation and the nondominated sorting genetic algorithm (NSGA-II) with theoretical model were developed to optimize the RDL via size. The results revealed that: (1) smaller via depth and size reduce the heat dissipation and thermal cycling reliability of the RDL via; (2) through both the ACO-BPNN and NSGA-II, the same optimal heat dissipation and plastic work density can be achieved in the designed module. (3) ACO-BPNN with assist of finite element simulation can provide a more effective optimization in complex packaging structure.@en

Power devices are developing for the small volume, high performance and modularization. With more and more application scenarios of Brushless Direct Current Motor (BLDC), MOSFET multi-chip module (MCM) is popular with people. However, the conventional wire Bonding and Copper clip welding technology struggles to meet the requirements for the excessive heat accumulation and complex logic problems in MCM. While the above problems can be well solved by using the new Fan out panel level packing(FOPLP) technology for QFN packaging of multi-chip. The traditional welding technology is used at the bottom of the chip, and the copper porous link is used at the top of the chip with low parasitic capacitance, inductance and low Rdson in electrical performance. In respect to thermal management, the ?JC on the top of the chip can be reduced, which has the effect of double-sided heat dissipation. Top Layer interconnection technology is adopted in the packaging scheme, which can have complex circuit layout.This paper mainly describes the technical implementation of this packaging technology, adopting the finite element software to establish a three-dimensional model of a new type of FOPLP and wire welding packaging for MCM. The thermal resistance of different packaging schemes is calculated to confirm the advantages and disadvantages of different schemes by the way of thermal simulation, the internal temperature distribution of different packaging structures and the main influencing factors of the thermal resistance of packaging compared.

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