Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace’s equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments.@en

The increased switching frequency and speed of silicon carbide (SiC) MOSFETs lead to higher power density of inverters, but meanwhile resulting in weak electromagnetic interference (EMI). The impedance balance technique is a good way to reduce the common mode (CM) noise by making the voltage across the line impedance stabilization network (LISN) as small as possible. However, a side effect of this technique is the generation of relatively large loop current that circulates in the inverter. It can cause additional losses and cost, which can be a factor that stops the increase of the switching frequency by SiC MOSFET. This article, for the first time, analyzes the relationship between the CM noise and loop current of the three-level active neutral point clamped (ANPC) inverter, and proposes a co-reduction method for both. First, the CM noise and loop current are clarified for the ANPC inverter, and the analytical models for both are established. The conflict between the CM noise and loop current is introduced with a specific case by the existing design method. Then a co-reduction method is proposed and elaborated, which can both suppress the CM noise and the loop current. The extra cost and volume by the proposed method are also analyzed and are negligible. The design guideline is further shown for clarity. Finally, the analysis and proposed method is validated by the experiment.@en

The optimization of mesa etch for a quasi-vertical gallium nitride (GaN) Schottky barrier diode (SBD) by inductively coupled plasma (ICP) etching was comprehensively investigated in this work, including selection of the etching mask, ICP power, radio frequency (RF) power, ratio of mixed gas, flow rate, and chamber pressure, etc. In particular, the microtrench at the bottom corner of the mesa sidewall was eliminated by a combination of ICP dry etching and tetramethylammonium hydroxide (TMAH) wet treatment. Finally, a highly anisotropic profile of the mesa sidewall was realized by using the optimized etch recipe, and a quasi-vertical GaN SBD was demonstrated, achieving a low reverse current density of 10⁻⁸ A/cm² at −10 V.

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In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermo-mechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

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This paper presents a medium frequency transformer with high insulation level design which is used for the DAB DC-DC converter. The transformer size is largely reduced when operating at medium frequency compared with conventional power frequency transformer which provides the possibility for higher power density. However, there is a trade-off between the high power density and thermal performance. First of all, the exposed cooling surface is reduced accordingly. And the dissipated heat is proportional to the exposed cooling surface directly. Secondly with higher frequencies, effects such as skin and proximity and hysteresis losses are significantly increased compared to transformer operation at 50/60 Hz. Besides the design process should consider high isolation requirement. And this again defects the transformer thermal performance and this is because firstly insulation material adds extra losses to the system, secondly the construction of the insulation will block some cooling surfaces and thirdly those insulation materials normally have relatively low thermal conductivity. As a consequence, the thermal design should be carefully considered and evaluated. To solve this problem, only the high voltage side winding is impregnated in epoxy resin which reduces the insulation material. The stacked transformer cores are gapped from each other which have helped the transformer heat dissipation. Such that, a design with low thermal resistance and high power density is achieved. FEM models are developed to analyze the transformer electric and thermal performances. Finally prototypes are built and tested to verify our design concept.

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Gallium nitride (GaN)-based vertical power Schottky barrier diode (SBD) has demonstrated outstanding features in high-frequency and high-power applications. This paper reviews recent progress on GaN-based vertical power SBDs, including the following sections. First, the benchmark for GaN vertical SBDs with different substrates (Si, sapphire, and GaN) are presented. Then, the latest progress in the edge terminal techniques are discussed. Finally, a typical fabrication flow of vertical GaN SBDs is also illustrated briefly.@en