A new panel-level silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) power module was developed by using the fan-out and embedded chip technologies. To achieve the more effective thermal management and higher reliability under thermal cycling, a new optimization method called Ant colony optimization-back propagation neural network (ACO-BPNN) was developed for optimizing SiC modules, and contrast it with the Response Surface Method (RSM). First, the heat dissipations of SiC MOSFET with different redistribution layer (RDL) materials were simulated through the ANSYS finite element simulation. Then, the RSM was adopted to design the experiments for optimization. Third, the optimized design considering both junction temperature and thermal-mechanical stress is obtained using RSM and ACO-BPNN. The results show that: 1) compared with nano-silver, copper has a relatively good heat dissipation effect, but nano-silver has a better thermodynamic performance, and 2) ACO-BPNN can provide more accurate optimization results without having to construct a fitness function like RSM. After optimization, the thermal management and the thermal-mechanical stress can be improved by about 3% and 11%, respectively.

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The increased switching frequency and speed of silicon carbide (SiC) MOSFETs lead to higher power density of inverters, but meanwhile resulting in weak electromagnetic interference (EMI). The impedance balance technique is a good way to reduce the common mode (CM) noise by making the voltage across the line impedance stabilization network (LISN) as small as possible. However, a side effect of this technique is the generation of relatively large loop current that circulates in the inverter. It can cause additional losses and cost, which can be a factor that stops the increase of the switching frequency by SiC MOSFET. This article, for the first time, analyzes the relationship between the CM noise and loop current of the three-level active neutral point clamped (ANPC) inverter, and proposes a co-reduction method for both. First, the CM noise and loop current are clarified for the ANPC inverter, and the analytical models for both are established. The conflict between the CM noise and loop current is introduced with a specific case by the existing design method. Then a co-reduction method is proposed and elaborated, which can both suppress the CM noise and the loop current. The extra cost and volume by the proposed method are also analyzed and are negligible. The design guideline is further shown for clarity. Finally, the analysis and proposed method is validated by the experiment.@en

In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermo-mechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

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SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

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In this article, a microchannel thermal management system (MTMS) with the two-phase flow using the refrigerant R1234yf with low global warming potential is presented. The thermal test vehicles (TTVs) were made of either single or multiple thermal test chips embedded in the substrates, which were then attached to the MTMS. The system included two identical aluminum microchannel heat sinks (MHSs) connected in series in the cooling loop, which also consisted of a gas flowmeter, a miniature compressor, a condenser, a throttling device, and accessory measurement components. The experimental results showed that the thermal management system could dissipate a heat flux of 526 W/cm2 while maintaining the junction temperature below 120 °C. For SiC mosfet with a higher junction temperature, e.g., 175 °C, the current system is expected to dissipate a heat flux as high as about 750 W/cm2. The effects of the rotational speed of the compressor, the opening of the throttling device, TTV layout on MHS, and a downstream heater on the cooling performance of the system were analyzed in detail. The study shows that the present thermal management with a two-phase flow system is a promising cooling technology for the high heat flux SiC devices.

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In this paper, a novel fan-out panel-level printed circuit board (PCB) embedded package technology for silicon carbide (SiC) MOSFET power module is presented to address parasitic inductances, heat dissipation, and reliability issues that are inherent with aluminum wires used in conventional packaging scheme. To withstand high temperature beyond 175 °C and high voltage over 1.2 kV and improve thermomechanical reliability of the fan-out panel-level PCB embedded SiC power module, bismaleimide-triazine (BT) laminate and prepreg with high-temperature stability, high dielectric strength, coefficient of thermal expansion (CTE) matching with SiC, and high T-g are selected as PCB embedded package materials. Then, high-temperature stabilities, dielectric breakdown strength, and thermomechanical performances of the embedded materials are characterized. The experimental results show that the PCB embedded materials can withstand high temperature beyond 200 °C and a high voltage above 1.2 kV. T-g is as high as over 260 °C, and CTE is matching with SiC. Besides, in order to provide one guideline for the high-temperature and high-pressure laminating process during the PCB embedded SiC MOSFETs packaging, cure kinetics of BT prepreg are analyzed. The results show that 1-h curing time at 280 °C curing temperature and 2-h curing time at 210 °C curing temperature can ensure the full cure of the BT prepreg.

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In this work, an experimental study on the aluminum plate fin evaporator based on a compact two-phase cooling system for high heat flux electronic packages is presented. Single-chip and multi-chip wire-bonded thermal test vehicles (TTVs) were fabricated and assembled in the PCB grooves designed to emulate high heat flux sources. The issue of heat dissipation was addressed by applying the evaporator to the TTVs, respectively, to evaluate their thermal characteristics. It is found that, the evaporator system could dissipate over 380 W/cm² for the TTV1 while maintaining its temperature at about 90 °C. As the effective heat source area and thermal design power (TDP) increased, the maximum heat flux that the system could dissipate decreased given the same chip temperature rise. Furthermore, the addition of a second evaporator and heat source following the main evaporator, increased the dissipation of the system. As a result, an increase of 48 W/cm² in heat removal capacity was observed in our test system. Finally, the effect of the differential pressure between the condenser and the evaporator was investigated. The increase in the differential pressure could improve the heat dissipation capacity of the two-phase cooling system. The temperature of the TTV2 dropped by 19 °C when the differential pressure increased by 2.7 bar. It can be concluded that the compact two-phase cooling system is a promising solution for removing heat from high heat flux electric packages.

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In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.

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The diversified system requirements have been continuously growing to drive the development of a variety of new package styles. Wafer-Level Packaging (WLP) technology has drawn attention with its thinner package due to the removal of substrate and thus higher performance. With the greater design flexibility in having more I/Os, Fan-out Wafer Level Packaging (FOWLP) technology has proven to be a more optimal and promising solution. Infineon's eWLB was introduced as the first generation FOWLP technology. In the eWLB technology, die shift is the processing defect that the die moves from its default position result in the wire disconnection. Placing the dies at the preset pitch can compensate the die shift before die attach process. In this paper, the key factors to controlling die shift will be discussed, and the complex process capability index (Cpk) of process is 2.06 which represents the die shift can be well minimized after compensation.

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