SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

In this article, a microchannel thermal management system (MTMS) with the two-phase flow using the refrigerant R1234yf with low global warming potential is presented. The thermal test vehicles (TTVs) were made of either single or multiple thermal test chips embedded in the substrates, which were then attached to the MTMS. The system included two identical aluminum microchannel heat sinks (MHSs) connected in series in the cooling loop, which also consisted of a gas flowmeter, a miniature compressor, a condenser, a throttling device, and accessory measurement components. The experimental results showed that the thermal management system could dissipate a heat flux of 526 W/cm2 while maintaining the junction temperature below 120 °C. For SiC mosfet with a higher junction temperature, e.g., 175 °C, the current system is expected to dissipate a heat flux as high as about 750 W/cm2. The effects of the rotational speed of the compressor, the opening of the throttling device, TTV layout on MHS, and a downstream heater on the cooling performance of the system were analyzed in detail. The study shows that the present thermal management with a two-phase flow system is a promising cooling technology for the high heat flux SiC devices.

In this work, an experimental study on the aluminum plate fin evaporator based on a compact two-phase cooling system for high heat flux electronic packages is presented. Single-chip and multi-chip wire-bonded thermal test vehicles (TTVs) were fabricated and assembled in the PCB grooves designed to emulate high heat flux sources. The issue of heat dissipation was addressed by applying the evaporator to the TTVs, respectively, to evaluate their thermal characteristics. It is found that, the evaporator system could dissipate over 380 W/cm² for the TTV1 while maintaining its temperature at about 90 °C. As the effective heat source area and thermal design power (TDP) increased, the maximum heat flux that the system could dissipate decreased given the same chip temperature rise. Furthermore, the addition of a second evaporator and heat source following the main evaporator, increased the dissipation of the system. As a result, an increase of 48 W/cm² in heat removal capacity was observed in our test system. Finally, the effect of the differential pressure between the condenser and the evaporator was investigated. The increase in the differential pressure could improve the heat dissipation capacity of the two-phase cooling system. The temperature of the TTV2 dropped by 19 °C when the differential pressure increased by 2.7 bar. It can be concluded that the compact two-phase cooling system is a promising solution for removing heat from high heat flux electric packages.

In this paper, a novel fan-out panel-level printed circuit board (PCB) embedded package technology for silicon carbide (SiC) MOSFET power module is presented to address parasitic inductances, heat dissipation, and reliability issues that are inherent with aluminum wires used in conventional packaging scheme. To withstand high temperature beyond 175 °C and high voltage over 1.2 kV and improve thermomechanical reliability of the fan-out panel-level PCB embedded SiC power module, bismaleimide-triazine (BT) laminate and prepreg with high-temperature stability, high dielectric strength, coefficient of thermal expansion (CTE) matching with SiC, and high T-g are selected as PCB embedded package materials. Then, high-temperature stabilities, dielectric breakdown strength, and thermomechanical performances of the embedded materials are characterized. The experimental results show that the PCB embedded materials can withstand high temperature beyond 200 °C and a high voltage above 1.2 kV. T-g is as high as over 260 °C, and CTE is matching with SiC. Besides, in order to provide one guideline for the high-temperature and high-pressure laminating process during the PCB embedded SiC MOSFETs packaging, cure kinetics of BT prepreg are analyzed. The results show that 1-h curing time at 280 °C curing temperature and 2-h curing time at 210 °C curing temperature can ensure the full cure of the BT prepreg.

In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.

The diversified system requirements have been continuously growing to drive the development of a variety of new package styles. Wafer-Level Packaging (WLP) technology has drawn attention with its thinner package due to the removal of substrate and thus higher performance. With the greater design flexibility in having more I/Os, Fan-out Wafer Level Packaging (FOWLP) technology has proven to be a more optimal and promising solution. Infineon's eWLB was introduced as the first generation FOWLP technology. In the eWLB technology, die shift is the processing defect that the die moves from its default position result in the wire disconnection. Placing the dies at the preset pitch can compensate the die shift before die attach process. In this paper, the key factors to controlling die shift will be discussed, and the complex process capability index (Cpk) of process is 2.06 which represents the die shift can be well minimized after compensation.

Nowadays, fan-out package is regarded as one of the latest and most potential technologies because it possesses lower cost, thinner profile, and better electrical performance and thermal performance. However, thermally induced warpage in the molding process is a critical issue due to the larger wafer or panel size, the shrinkage of epoxy mold compound (EMC) during the curing stage, and the mismatch of coefficient of thermal expansion (CTE) among the constituent materials during the cooling stage, which needs to be controlled effectively for successful subsequent process of the fan-out package. In this paper, a novel $320 x 320$-mm² panel-level fan-out package based on ``Die Last'' process is developed. A coreless substrate with redistribution layer is fabricated and bonded onto a low-CTE and high-glass-transition-temperature (Tg) FR4 carrier through thermal release film. The thermally induced warpage issue in the molding process is investigated. A warpage simulation method is presented and verified by Shadow Moiré experiment. The error between the simulation and experimental results is about 4.8%. For the warpage optimization analysis, the effect of geometry structure on the warpage is first investigated by the design of simulation approach. Full factor experiment is conducted, and Minitab statistical software is utilized to analyze the effect of the geometry structure on warpage. It is found that decreasing die thickness and molding thicker EMC can effectively decrease the warpage. Then, the effects of molding temperature and in-plane CTE of FR4 on warpage are studied, respectively. When molding temperature is 120 °C and in-plane CTE of FR4 decreases to 10.5 ppm/°C, the thermally induced warpage in the molding process is only about 0.31 mm, thus subsequent process of fan-out package can be conducted successfully.