Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace’s equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments.@en

This work employed the particle swarm optimization (PSO) algorithm to assess the trade-off between breakdown voltage (BV) and on-state resistance (R DS,on ) in 4H–SiC metal oxide semiconductor field effect transistors (MOSFET) for power devices. In this work, the numerical model obtained after analyzing the resistance composition is utilized as the objective function in PSO to determine characteristic parameters in double-diffused metal oxide semiconductor field effect transistors (DMOSFET). These equations are input for the PSO algorithm. The derived characteristic parameters include the drift region doping concentration and thickness, cell size, channel length, JFET region length, JFET region thickness, and doping concentration. To adhere to common application constraints, this work optimizes these characteristic parameters to minimize the R DS,on under typical BV ranging from 100 to 2000 V. The R DS,on for some typical applications was extracted and validated through TCAD simulations to ensure algorithm accuracy. The reported results confirm that PSO yields superior outcomes and may be considered when designing devices. This work offers helpful insights into the design of characteristic parameters for 4H–SiC power DMOSFET devices and evaluates the feasibility of using PSO to optimize the characteristic parameters of power devices.

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With the increased deployment of power modules in demanding conditions, sintering materials, especially composite sintering materials, have raised growing interest due to their cost-effectiveness and suitability. Therefore, this study explores the viability of Cu–Ag composite sintering material, focusing on solvent influence through microstructure and mechanical behavior analysis. Micron-sized particle-based Cu–Ag composite pastes were designed and compared using eight solvents (four epoxy-free and four epoxy-added) based on fluidity and thermal stability. The sintered joints' performance, assessed through shear strength analysis, showed comparable values to pure silver sintering for both epoxy-free and epoxy-added samples. Optimized samples from each solvent system underwent reliability analysis, demonstrating that Cu–Ag joints with epoxy resin exhibited significantly higher shear strength after high-temperature storage and thermal cycling tests. Micromorphology and elemental composition analysis revealed differences in aging mechanisms, primarily attributed to variations in porosity due to oxide formation and pore filling by epoxy resin under different solvent systems. Further nanoindentation characterization of micromechanical properties, including hardness, modulus, and creep properties, during high-temperature aging, established constitutive models for insights into reliability evolution. In conclusion, the optimized epoxy-added Cu–Ag sintered joints proposed in this study demonstrated exceptional reliability and acceptable micromechanical properties, presenting a promising option for high-temperature power packaging.

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A fan-out panel-level packaging (FOPLP) with an embedded redistribution layer (RDL) via interconnection reduces the size, thermal resistance, and parasitic inductance of power module packaging. In this study, the effect of the RDL via size on the reliability of a FOPLP SiC MOSFET power module was investigated. To improve the thermal management and thermal cycling reliability of the designed SiC module, genetic algorithm (GA)–assisted optimization methods were proposed to optimize the RDL via size. First, the heat dissipation and the plastic work density of the SiC MOSFET module with various via diameters and depths were simulated using finite element simulations. Next, both the ant colony optimization-backpropagation neural network (ACOBPNN) with finite element simulation and the nondominated sorting genetic algorithm (NSGA-II) with theoretical model were developed to optimize the RDL via size. The results revealed that: (1) smaller via depth and size reduce the heat dissipation and thermal cycling reliability of the RDL via; (2) through both the ACO-BPNN and NSGA-II, the same optimal heat dissipation and plastic work density can be achieved in the designed module. (3) ACO-BPNN with assist of finite element simulation can provide a more effective optimization in complex packaging structure.@en

The wide-bandgap semiconductors represented by GaN have a broad application prospect because of their high service temperature and high switch frequency. Quad-Flat-No-Lead (QFN) Package is currently one of the mainstream packaging methods due to its low cost and high efficiency. However, the low reliability of QFN used in GaN devices is still a crucial problem caused by elevated temperatures and the thermal stress induced by the mismatch of coefficient of thermal expansion (CTE). Therefore, it is necessary to control the temperature inner the package and increase the mechanical property of the bonding layer. In this paper, the finite element method (FEM) with thermal-mechanical coupling is performed to optimize the reliability of the bonding layer by adopting sinter nano Cu and silver. Based on the conventional QFN package module, we tried to add different metallization on the bonding surface to decrease the influence of CTE mismatch. We should note that the Anand viscoplastic model was used in the materials of Sintered Ag and lead-free solder paste presented by SAC305, which were the most commonly used in die-attachment. The results showed that the utilization of nano copper/silver paste could hardly facilitate thermal performance although sintered Ag had excellent thermal conductivity. Since the Anand modules of Ag and SAC305 were different, there were some impacts on the stress distribution and deformation. During the bonding process, a large thermal stress generated between die-attachment layer and Package or the PCB. The die-attachment layer formed by nano Ag paste suffered the smaller thermal stress because its CTE is comparable to that of thermal pad. In terms of sintered Ag, the bonding layer generated more elastic strain. As the deformation recovered to initial stage, the stress decreased because of the elastic strain. And we also found that the Ag metallization could decreased the maximum stress of model at heating stage. But Ag metallization suffered larger thermal stress as the temperature decreased. The selection of connection materials and metallization are a crucial part of design the structure of electronic package. And this paper could provide a reference for optimize the package structure to further improve their reliability in future works.

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Nano-copper sintering is one of new die-attachment and interconnection solutions to realize the wide bandgap semiconductor power electronics packaging with benefits on high temperature, low inductance, low thermal resistance and low cost. Aiming to assess the high-temperature reliability of sintered nano-copper die-attachment and interconnection, this study characterized the mechanical properties of sintered nano-copper particles using the high-temperature nanoindentation tests. The results showed that: firstly, the hardness and indentation modulus of the sintered nano-copper particles increased rapidly when the loading rate increased below 0.2 mN·s⁻¹ and then stabilized, and decreased with increased applied load up to 30 mN. Next, by extracting the yield stress and strain hardening index, a plastic stress–strain constitutive model at room temperature for sintered nano-copper particles was obtained. Finally, the high temperature nanoindentation tests were performed at 140 ˚C–200 ˚C on the sintered nano-copper particles prepared under different assisted pressures, which showed that a high assisted pressure resulted in the reduced temperature sensitivity of hardness and indentation modulus. The creep tests indicated that high operation temperature resulted in a high steady-state creep rate, which negatively impacted the creep resistance of sintered nano-copper particles, while the higher assisted pressure could improve the creep resistance.

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Light-emitting diodes (LEDs) are among the key innovations that have revolutionized the lighting industry, due to their versatility in applications, higher reliability, longer lifetime, and higher efficiency compared with other light sources. The demand for increased lifetime and higher reliability has attracted a significant number of research studies on the prognostics and lifetime estimation of LEDs, ranging from the traditional failure data analysis to the latest degradation modeling and machine learning based approaches over the past couple of years. However, there is a lack of reviews that systematically address the currently evolving machine learning algorithms and methods for fault detection, diagnostics, and lifetime prediction of LEDs. To address those deficiencies, a review on the diagnostic and prognostic methods and algorithms based on machine learning that helps to improve system performance, reliability, and lifetime assessment of LEDs is provided. The fundamental principles, pros and cons of methods including artificial neural networks, principal component analysis, hidden Markov models, support vector machines, and Bayesian networks are presented. Finally, discussion on the prospects of the machine learning implementation from LED packages, components to system level reliability analysis, potential challenges and opportunities, and the future digital twin technology for LEDs lifetime analysis is provided.

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