A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

Abstract

SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of $8\times {8} \times {0}.{75}$ mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain-source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 °C/W; and 3) after 2000 thermal cycling cycles, drain-source ON-state resistance [RDS(on)] increased by less than 2%, which revealed the higher reliability of the package under thermal cycling.