Coherent links between qubits separated by tens of micrometers are expected to facilitate scalable quantum computing architectures for spin qubits in electrically defined quantum dots. These links create space for classical on-chip control electronics between qubit arrays, which can help to alleviate the so-called wiring bottleneck. A promising method of achieving coherent links between distant spin qubits consists of shuttling the spin through an array of quantum dots. Here, we use a linear array of four tunnel-coupled quantum dots in a 28Si/SiGe heterostructure to create a short quantum link. We move an electron spin through the quantum dot array by adjusting the electrochemical potential for each quantum dot sequentially. By pulsing the gates repeatedly, we shuttle an electron forward and backward through the array up to 250 times, which corresponds to a total distance of approximately 80μm. We make an estimate of the spin-flip probability per hop in these experiments and conclude that this is well below 0.01% per hop.

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Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

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Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

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Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a ²⁸Si/²⁸SiO₂ interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.

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The discovery of the counter-intuitive laws of quantum mechanics at the beginning of the 20th century revolutionized physics. Quantum-mechanical properties, such as superposition and entanglement, can be harnessed to create quantum technology that opens a computing power far beyond the computing power that we know today. A quantum computer would enable efficient simulations of chemical reactions and material properties, which is expected to greatly impact healthcare and the energy transition. Practical quantum computation requires millions of qubits, either with neighbour-to-neighbour connectivity, or connected via quantum links. Spin qubits in electrically-defined silicon quantum dots are promising qubit candidates due to their small footprint and relatively long coherence time. The last decade meant a leap for the understanding and control of spin qubit systems with devices up to three quantum dots. Yet building systems capable of performing useful quantum calculations has proven difficult due to low sample yield, as well as challenges in controlling and scaling these systems. In this thesis, we explore quantum-dot-based spin qubits and their suitability for scaling to larger systems. This quest was threefold and can be summarized as: More, Distant, Industrial. - More: Increasing the number of quantum dots and thus qubits to numbers greater than three was proven challenging, among others due to the the cross-capacitance that was posed upon quantum dots by the metallic gate electrodes of their neighbours. Here, we develop a material platform-independent method to individually control the chemical potential of each quantum dot and the number of electrons in it without affecting the quantum dots in their vicinity. We demonstrate the method by tuning up a linear array of eight GaAs quantum dots, containing exactly one electron each. - Distant: Thereafter, we shift our focus to creating quantum links between distant quantum dots by shuttling electron spins across a chip. Given the superior spin coherence times, we moved to silicon quantum dots, which were not as far developed at the time. To improve our understanding of the material and allow for the fabrication of silicon arrays beyond two quantum dots, we formulate metrics that allow for sample comparison across material platforms and gate geometries, which allows us to examine samples and detect disorder and flaws to improve (uniform) sample fabrication. This enables the fabrication of a sample that can host an array of up to five quantum dots and tune it with the method described above. To mimic a quantum link, we shuttle an electron forth and back through four quantum dots of the array up to 1000 times, corresponding to a total distance travelled of approximately 80 _m. We observe that the spin orientation was preserved, forming a promising base for a quantum link. - Industrial: Thirdly, in collaboration with Intel, we harness the experience of the semiconductor industry by industrially manufacturing quantum chips and controlling a qubit on these chips. By means of the metrics that we defined, we demonstrate that industrial manufacturing on 300-mm wafers allows for high yield and reasonable cross-wafer uniformity of the samples, while allowing for well-defined quantum dots and qubits with a performance that is comparable to state-of-the-art spin-qubit results. This high-yield fabrication without compromising qubit properties is crucial for scaling to the thousands of qubits that we need for practical quantum computation. The results in this dissertation provide perspective for scaling up silicon quantum dots and position the silicon spin qubit as a primary candidate for achieving quantum advantage with large-scale devices with millions of qubits. @en

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

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Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a ²⁸ Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

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Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

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Electrostatically defined quantum dot arrays offer a compelling platform for quantum computation and simulation. However, tuning up such arrays with existing techniques becomes impractical when going beyond a handful of quantum dots. Here, we present a method for systematically adding quantum dots to an array one dot at a time, in such a way that the number of electrons on previously formed dots is unaffected. The method allows individual control of the number of electrons on each of the dots, as well as of the interdot tunnel rates. We use this technique to tune up a linear array of eight GaAs quantum dots such that they are occupied by one electron each. This new method overcomes a critical bottleneck in scaling up quantum-dot based qubit registers.

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We report on the fabrication and characterization of a Fabry-Perot microcavity enclosing a thin diamond membrane at cryogenic temperatures. The cavity is designed to enhance resonant emission of single nitrogen-vacancy centers by allowing spectral and spatial tuning while preserving the optical properties observed in bulk diamond. We demonstrate cavity finesse at cryogenic temperatures within the range of F ¼ 4000–12 000 and find a sub-nanometer cavity stability. Modeling shows that coupling nitrogen-vacancy centers to these cavities could lead to an increase in remote entanglement success rates by three orders of magnitude.@en