Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a ²⁸Si/²⁸SiO₂ interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.

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One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.

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To harness the potential of quantum mechanics for quantum computation applications, one of the main challenges is to scale up the number of qubits. The work presented in this dissertation is concerned with several aspects that are relevant in the quest of scaling up quantum computing systems based on spin qubits in silicon. Few-qubit experiments are maturing quickly, but simultaneously the lacuna between them and large-scale quantum computers is filled with a combination of science and engineering challenges. The challenges that are addressed in this dissertation are reliable and reproducible sample fabrication, qubit resilience to temperature, spatial correlations in the noise affecting the qubits, and co-integration of qubits with classical control electronics. I start with describing the development of an integration scheme for silicon spin qubits in an academic cleanroom environment, as several research groups have demonstrated over the last years. This has allowed them to successfully fabricate and operate silicon spin qubit devices. The development of such a scheme is crucial for the fabrication of proof-of-principle devices, and the testing of several design variations for more and more complex qubit devices, before transferring the optimal designs to industrial foundries that are generally less flexible. Moreover, it is essential for performing paramount few-qubit experiments in the near term. The developed scheme has been successfully implemented in the next chapter of this thesis. In the first experiment, we investigate the effect of temperature on the spin lifetime, as a first step towards higher temperature operation of silicon spin qubits. Spin qubit operation at elevated temperatures will be required to allow for co-integration of qubits with classical control electronics on a single chip, since the heat load associated with this electronics will be too much to deal with at the current qubit operation temperature of ∼10 mK. At a temperature of ∼1-4 K, significantly more cooling power is available (see for example CERN's Large Hadron Collider). Such co-integration would alleviate the interconnect bottleneck and facilitate the implementation of local control in large-scale devices. We find only a modest temperature dependence and measure a spin relaxation time of 2.8 ms at 1.1 K (still much longer than the record spin dephasing time measured in such a system). In addition, we present a theoretical model and use it in combination with our experimentally obtained parameters to demonstrate that the spin relaxation time can be enhanced by low magnetic field operation and by employing high-valley-splitting devices. Together with more recent work, this experiment demonstrates no fundamental limitations to prevent high-temperature operation of silicon spin qubits. Simultaneously, bringing classical control electronics to lower temperatures also is an active research area. The second experiment uses maximally entangled Bell states of two qubits to study spatial correlations in the noise acting on those two qubits. Spatial correlations in qubit errors hinder quantum error corrections schemes that will be required for fault-tolerant large-scale quantum computers, as these schemes are commonly derived under the assumption of negligible correlations in qubit errors. Therefore, it is important to know to what extent the noise causing these errors is correlated. We find only modest spatial correlations in the noise and gain insight in their origin. The data is in accordance with decoherence being dominated by a combination of nuclear spins and multiple distant charge fluctuators coupling asymmetrically to the two qubits. We recommend to perform similar experiments in isotopically purified silicon to eliminate the effect of nuclear spins and in isolation study spatial correlations in charge noise. Furthermore, our insights show how correlations can be either maximized or minimized through qubit device design. For these reasons, the prospects for the development and implementation of quantum error correction schemes in fault-tolerant large-scale quantum computers are promising. Finally, after having studied several aspects that are relevant to determine the suitability of silicon spin qubits for large-scale quantum computation in the preceding experiments, we propose a concrete physical implementation of co-integrated spin qubits with classical control electronics in a sparse spin qubit array. While the community usually claims compatibility of silicon spin qubits with conventional CMOS fabrication, existing proposals make assumptions that remain to be validated. Implementing quantum error correction protocols in a sparse array has been studied, but the description of a physical implementation was largely missing. The sparseness of the array allows for integration of local control electronics, as shown to be promising earlier in this thesis. Specifically, we propose to implement sample-and-hold circuits alongside the qubit circuitry that would allow to offset inhomogeneity in the qubit array. This enables individual local control and shared global control, resulting in an efficient line scaling. The scalable unit cell design fits 220 (≈106) qubits in ∼150 mm2. We assess the feasibility of the proposed scheme, as well as its physical implementation and the associated footprint, line scaling and interconnect density.@en

We study spatial noise correlations in a Si/SiGe two-qubit device with integrated micromagnets. Our method relies on the concept of decoherence-free subspaces, whereby we measure the coherence time for two different Bell states, designed to be sensitive only to either correlated or anticorrelated noise, respectively. From these measurements we find weak correlations in low-frequency noise acting on the two qubits, while no correlations could be detected in high-frequency noise. We expect nuclear spin noise to have an uncorrelated nature. A theoretical model and numerical simulations give further insight into the additive effect of multiple independent (anti)correlated noise sources with an asymmetric effect on the two qubits as can result from charge noise. Such a scenario in combination with nuclear spins is plausible given the data and the known decoherence mechanisms. This work is highly relevant for the design of optimized quantum error correction codes for spin qubits in quantum dot arrays, as well as for optimizing the design of future quantum dot arrays.

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Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with standard semiconductor manufacturing and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technology and identify industrial qubits, hybrid technology, automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation.

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Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

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We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.

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Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a ²⁸ Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

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We investigate the magnetic field and temperature dependence of the single-electron spin lifetime in silicon quantum dots and find a lifetime of 2.8 ms at a temperature of 1.1 K. We develop a model based on spin-valley mixing and find that Johnson noise and two-phonon processes limit relaxation at low and high temperature, respectively. We also investigate the effect of temperature on charge noise and find a linear dependence up to 4 K. These results contribute to the understanding of relaxation in silicon quantum dots and are promising for qubit operation at elevated temperatures.

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Quantum computing holds the promise of exponential speedup compared to classical computing for select algorithms and applications. Relatively small numbers of logical quantum bits or qubits could outperform the largest of supercomputers. Quantum dots in Si-based heterostructures and superconducting Josephson junctions are just two of the many approaches to construct the qubit. These, in particular, bear similarities to the transistors and interconnects used in advanced semiconductor manufacturing. While initial results on few-qubit systems are promising, advanced process control is expected to improve the qubit uniformity, coherence time, and gate fidelity needed for larger systems. This can be realized through the systematic characterization of film growth, interface control, and patterning.

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