Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

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As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

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Future quantum computers capable of solving relevant problems will require a large number of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State preparation combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.

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Spin qubits in silicon have emerged as a promising candidate for a scalable quantum computer due to their small footprint, long coherence times, and their compatibility with advanced semiconductor manufacturing. However, all known spin qubit material hosts come with specific challenges, that limit the performance of quantum information processing. In this thesis we study Si/SiGe heterostructures, comprising a strained silicon (Si) quantum well which is sandwiched between two silicon-germanium (SiGe) barriers. Si/SiGe heterostructures designed to act as solid-state matrix to host spin qubits have three intrinsic material challenges that limit performance: hyperfine interaction, valley splitting, and charge noise. Therefore, to realize a scalable quantum computer in Si/SiGe heterostructures we first quantify the performance limiting parameters and subsequently, we improve them systematically with statistical significance. Acquiring data with statistical significance, however proves challenging for quantum devices in Si/SiGe heterostructures due to complicated and time-consuming fabrication schemes for device manufacturing, and the need of using dilution refrigerators that cool samples down to sub-Kelvin temperatures with only a limited amount of wires for electrical characterization of devices. Therefore, in this thesis we demonstrate fast growth-fabrication-measurement feedback cycles to accelerate our understanding on the materials and devices. We realize such fast feedback cycles by first establishing a unique workflow at TU Delft, allowing 100~mm wafer growth and fabrication. Subsequently in our first experiment, we overcome the wiring bottleneck by presenting a cryogenic multiplexing platform that multiplies DC wires inside of a dilution refrigerator. This cryogenic multiplexer platform uses commercially available CMOS components, is compatible with any dilution refrigerator, and allows us to measure thirteen chips in the same cooldown at a temperature of 50~mK and at magnetic fields of up to 10~T. We confirm these extreme measurement conditions by showing statistically significant quantum transport properties of industrially grown 300~mm $^{ ext{nat}}$Si/SiGe wafers. In the following experimental chapters we then leverage the cryogenic multiplexer to successively tackle the performance limiting parameters of spin qubit processors in Si/SiGe heterostructures. In the second experiment we first analyze valley splitting in two dimensional electron gases and observe that valley splitting increases linearly with the electric field at the quantum Hall edge states of the device at a rate consistent with theoretical predictions. In turn, this observation allows us to evaluate valley splitting on a micron length scale with relatively simple Hall-bar measurements. In the third experiment we show two major improvements in our heterostructures. First, we measure valley splitting in quantum dots with varying quantum well interface sharpness with statistical significance. We then proceed to analyze the atomic composition of the quantum well interfaces in several samples using atom probe tomography and show that Ge atoms are distributed randomly in each atomic layer. Subsequently using the atom probe tomography results as input, we simulate valley splitting and show that valley splitting depends on the atomistic details of the interface and needs to be treated as a statistical distribution. We then propose a strategy to increase valley splitting on average above a chosen threshold by introducing a small concentration of Ge atoms into the quantum well. Second, all electrical measurements in this experiment are performed in isotopically purified $^{28}$Si quantum wells, which reduces the hyperfine interaction and hence increases qubit coherence times. While we do not explicitly discuss this improvement in this chapter, it is a crucial baseline for all following experiments in this thesis and for all qubit experiments using Delft grown $^{28}$Si/SiGe heterostructures. We then move to show wafer-scale improvements of the disorder landscape of Si quantum wells in our fourth experiment. There, we challenge the common approach of growing an epitaxial Si cap on the $^{28}$Si/SiGe heterostructure, by replacing the Si cap with an amorphous Si-rich layer. We compare these two heterostructues by monitoring the statistical performance of mobility, percolation density, maximum electric field before hysteresis, and single particle relaxation time and observe a statistical performance increase of the mean value and the standard deviation. In the fifth experiment we study a heterostructure with a thin quantum well and compare its statistical performance of mobility, percolation density, and charge noise with the performance of the heterostructures from the preceding experiment. Importantly, we find that misfit dislocation arising from strain relaxation are significantly reduced in thin quantum wells as confirmed by geometrical phase analysis of transmission-electron microscope images. In consequence, we observe a statistical performance increase of all key metrics in the novel heterostructure, only possible by our approach of engineering the critical material layers. Finally, we see promising simulated qubit coherence times and qubit error rates when using our charge noise results as simulation input, hinting at a practical advantage of our novel $^{28}$Si/SiGe heterostructures for quantum processors. In the last experimental chapter we demonstrate how our improved $^{28}$Si/SiGe heterostructures have enabled two key experiments in the field of spin-based quantum computing. First, we show that our purified heterostrucures may host high-quality qubits, that in turn serve as a testbed for demonstrating CMOS-based cryogenic control of silicon quantum circuits. Second, we show how our isotopically purified, low-disorder heterostructures host a 6-qubit quantum processor with high-fidelity initialization, high-fidelity gate operation, and high-fidelity readout. We conclude this thesis by highlighting key improvements of our $^{28}$Si/SiGe hetero-structures that have contributed to state-of-the-art spin qubit experiments. However, our heterostructures still require further improvements if we want to achieve error rates around 10$^{-6}$ and scale to large spin qubit arrays with more than a million qubits. Therefore, we discuss additional material changes that could further lower spin qubit error rates and we consider how to assess the uniformity of the material over different length scales, relevant when striving for larger qubit arrays. @en

Atom probes generate three-dimensional atomic-scale tomographies of material volumes corresponding to the size of modern-day solid-state devices. Here, the capabilities of atom probe tomography are evaluated to analyze buried interfaces in semiconductor heterostructures relevant for electronic and quantum devices. Employing brute-force search, the current dominant reconstruction protocol to generate tomographic three-dimensional images from Atom Probe data is advanced to its limits. Using Si/SiGe heterostructure for qubits as a model system, the authors show that it is possible to extract interface properties like roughness and width that agree with transmission electron microscopy observations on the sub-nanometer scale in an automated and highly reproducible manner. The demonstrated approach is a versatile method for atomic-scale characterization of buried interfaces in semiconductor heterostructures.

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We grow 28Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, 28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8 ± 0.5) × 10 5 cm2/V s and a low mean percolation density of (9 ± 1) × 10 10 cm-2. From the analysis of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1 ± 0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5 ± 0.6) × 10 4 cm2/V s and (40 ± 3) μ eV, respectively, and a small mean Dingle ratio of (2.3 ± 0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.

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Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

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The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications¹. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)². When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’^3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots^7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm¹⁰, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

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Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with standard semiconductor manufacturing and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technology and identify industrial qubits, hybrid technology, automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation.

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We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined to low-disorder Si quantum wells. We probe the valley splitting dependence on both perpendicular magnetic field B and Hall density by performing activation energy measurements in the quantum Hall regime over a large range of filling factors. The mobility gap of the valley-split levels increases linearly with B and is strikingly independent of Hall density. The data are consistent with a transport model in which valley splitting depends on the incremental changes in density eB/h across quantum Hall edge strips, rather than the bulk density. Based on these results, we estimate that the valley splitting increases with density at a rate of 116 μeV/1011 cm-2, which is consistent with theoretical predictions for near-perfect quantum well top interfaces.

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Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology, we accelerate the development of 300 mm epitaxial wafers manufactured in an industrial CMOS fab and report a remarkable electron mobility of (3.9 ± 0.6) × 10⁵ cm²/Vs and percolation density of (6.9 ± 0.4) × 10¹⁰ cm⁻², representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information, and because of the simplicity of assembly and versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

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