Abstract: At present, over 95% of the manufactured packages are still being wire-bonded. due to the ongoing trend of miniaturization, material changes, and cost reduction, wire-bond-related failures are becoming increasingly important. Different finite-element (FE) techniques are explored for their ability to describe the thermomechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multifailure-mode interaction accurately and efficiently. It is found that both processing and reliability-testing environments as well as the occurrence of delamination strongly increase the risk of wire failures. Our results indicate that processing and reliability-testing influences are much less than those of the delamination. Combining the strengths of predictive modeling with simulation-based optimization methods, the optimal wire-loop shape is obtained. Index Terms: Delamination, finite-element (FE) modeling, wire-bond reliability, wire-loop shape.@en

Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. Numerical modeling can provide more fundamental understanding of these failure phenomena. As a result, predicting and ultimately preventing these phenomena will result in an increased reliability of current and future electronic products. In this paper, delamination phenomena occuring in Cu/low-k back-end structures, buckling-driven delamination in flexible electronics and peeling tests on stretchable electronics will be modeled and validated by experimental results. For the Cu/low-k back-end structues, failure sensitivity analysis is performed by the recently developed Area Release Energy (ARE) method while transient delamination processes are described by cohesive zone elements in the critical regions. For the latter, a dedicated solver is applied that is able to deal with brittle interfaces. For the flexible and stretchable electronics applications, cohesive zones are used to characterize the interface properties by combining numerical results with experimental measurements.@en

We propose an amorphous/porous molecular connection network generation algorithm for simulating the material stiffness of a low-k material (SiOC:H). Based on a given concentration of the basic building blocks, this algorithm will generate an approximate and large amorphous network. The molecular topology is obtained by distributing these blocks randomly into a predefined framework. Subsequently, a structural relaxation step including local and global perturbations is applied to achieve the most likely stereochemical structure. Thus, the obtained mechanical properties of the low-k materials have been verified with the experimental data.@en

Purpose ¿ At present, over 95 percent of the manufactured packages are still being wire bonded. Owing to the ongoing trend of miniaturization, material changes, and cost reduction, wire bond-related failures are becoming increasingly important. This paper aims to understand these kinds of failures. Design/methodology/approach ¿ Different finite element (FE) techniques are explored to their ability to describe the thermo-mechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multi-failure mode interaction accurately and efficiently. Findings ¿ It is found that both processing and testing environments as well as the occurrence of delamination strongly increase the risk for wire failures. The results indicate that processing and testing influences are much less than those of the delamination. Practical implications ¿ Package designers should focus on limiting the occurrence of delamination around wire bond and/or stitch areas. Originality/value ¿ Combining the strengths of predictive modeling with simulation-based optimization methods, the optimal wire shape is obtained.@en

The mechanical stiffness of the silica nano-structures, including the crystalline silicon and amorphous silica, is studied using the molecular dynamics (MD) method. The MD simulation procedure is based on the linear-elastic theory, and the stiffness parameter can be acquired by the reaction forces of the sample. Moreover, we also propose a molecular structure generation algorithm for the amorphous silica, which is a low-dielectric material (SiOC:H). In the simulation of crystalline silicon, the results show good approach to the experimental results and the size effect of the nano-structures was captured. Moreover, the simulation of amorphous silica, the trends which are indicated by the simulation results exhibit good agreements with the ones by the experiment. Keywords: molecular dynamics, atomistic modeling, mechanical stiffness, amorphous material.@en

We propose an atomic simulation technique to understand the chemical-mechanical relationship of amorphous/porous silica based low-dielectric (low-k) material (SiOC(H)). The mechanical stiffness of the low-k material is a critical issue for the reliability performance of the IC backend structures. Due to the amorphous nature of the low-k material which has till now unknown molecular structure, a novel algorithm is required to generate the molecular structure. The molecular dynamics (MD) method is used as the simulation tool. Moreover, to understand the variation of the mechanical stiffness and density by the chemical configuration, sensitivity analyses have been performed. A fitting equation based on homogenization theory is established to represent the MD simulation results. The trends which are indicated by the simulation results exhibit good agreements with experiments from literature. Moreover, the simulation results indicate that the slight variation of the chemical configuration can induce significant change of the mechanical stiffness (over 80%) but not the density.@en

For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-k back-end structures. The obtained results are in good agreement with experimental observations.@en

In this paper, the material stiffness of amorphous/porous low-k material and interfacial strength between amorphous silica and low-k have been simulated by the molecular dynamics (MD) methods. Due to the low stiffness of the low-k material, the interfaces which include this material are critical for the most delamination and reliability issues around the IC back-end structure. MD simulation technique is applied to elucidate the crack/delamination mechanism at these critical interfaces. However, due to the amorphous nature of the low-k material (eg. SiOC:H), the atomic modeling technique of the amorphous/porous silica is first established. Through the experimental validation, the accuracy of this amorphous modeling technique is obtained, and the results show that this algorithm can represent the trend of the mechanical stiffness change due to different chemical composition of low-k material. A novel interfacial modeling technique, which models the status of chemical bonds at interface during the delamination loading, is developed. Afterward, the simulation of the mechanical strength of the amorphous silica/SiOC:H interface, is implemented. The simulation depicts that the existence of the strong Si-O covalent bond will significantly enhance the adhesive strength of the interface. Instead of the covalent bond at interface, the simulation results also reveal the multiple atomic scaled crack path within the material during the interfacial delamination. Hence, improving the material stiffness of the soft low-k material and preventing the pore at interface can increase the adhesive strength of the silica/low-k interfacial system.@en

This paper presents our effort to predict IC, packaging, and board level reliability problems. Micro-electronic based reliability problems are driven by the mismatch between the different material properties, such as thermal expansion, hygro-swelling, and/or the degradation of interfacial strength. In the past, such reliability problems were treated separately, but recent developments have made clear that total product reliability concerns the interaction of IC, package, and PCB. This paper presents parts of our strategy to assess this integrated reliability by combining experimental and numerical techniques.@en

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.@en