Delamination Analysis of Cu/low-k Technology Subjected to Chemical-Mechanical Polishing Process Conditions

Journal article (2006)

Authors

C.A. Yuan Computational Design and Mechanics - Mechanical, Maritime and Materials Engineering
W.D. van Driel Dynamics of Micro and Nano Systems - Mechanical, Maritime and Materials Engineering
RBR van Silfhout External organisation
O van der Sluis Computational Design and Mechanics - Mechanical, Maritime and Materials Engineering
RAB Engelen External organisation
L.J. Ernst Computational Design and Mechanics - Mechanical, Maritime and Materials Engineering
A. van Keulen Computational Design and Mechanics - Mechanical, Maritime and Materials Engineering
Kouchi Zhang Computational Design and Mechanics - Mechanical, Maritime and Materials Engineering
Research Group
Computational Design and Mechanics (Mechanical, Maritime and Materials Engineering) (TU Delft)
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Published Date

2006

Language

Undefined/Unknown

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Faculty

Mechanical, Maritime and Materials Engineering

Department

Precision and Microsystems Engineering

Research Group

Computational Design and Mechanics

Abstract

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.