Olfactory learning in Drosophila larvae exemplifies efficient neural processing in a small-scale network with minimal power consumption. This system enables larvae to anticipate important outcomes based on new and familiar odor stimuli, a process crucial for survival and adaptation. Central to this learning mechanism is the olfactory pathway model, which embodies the principles of synaptic plasticity and associative learning through prediction error coding mediated by specific neuromodulating neurons in the mushroom body, like dopaminergic neurons. There is a pressing need to develop novel computational frameworks that capture the spatio-temporal processes while remaining compatible with the constraints of small-scale neural networks. These frameworks should draw inspiration from the biophysical properties of neurons within the olfactory pathway model, enabling accurate emulation of neural dynamics and efficient learning processes using spiking neural networks. This thesis proposes a framework based on a phenomenological conductance-based leaky integrate-and-fire (COBALIF) neuron model, inspired by the olfactory pathway model of Drosophila larvae. By first prototyping the spiking neural network in Intel's Lava Python-based framework, we validated the design on a neuron and system level for a neuromorphic hardware implementation. This was the foundation of a programmable, neuromorphic FPGA architecture capable of adaptive optimization, employed on a Zynq 7000 SoC FPGA. By implementing this architecture in a single-precision floating-point format, we model the real-time neural dynamics of the COBALIF neuron in one-tenth of a millisecond precision. Moreover, our FPGA implementation serves as a feasible prototype for deploying such biologically inspired neurons and their spatio-temporal dependencies in digital design, paving the way for scaling up to small-scale networks.

To support the exploration of the Moon, wireless sensor networks could be deployed. However, using a very large number of tiny sensing nodes to collect data in such a harsh environment has many challenges. Integrated circuits are exposed to a wide temperature range (-253 °C / +120 °C) during the lunar days and nights. To meet the very constrained power budget of an autonomous node, the node time references must consume ultra-low power while maintaining an accurate frequency. To allow accurate operation over the wide target temperature range and be robust to radiations, this thesis proposes to lock the frequency of a frequency locked loop (FLL) to an LC filter. In the FLL, a high-frequency low-power ring oscillator is locked to a separate LC filter to potentially save power with respect of a standard LC oscillator. To further save power, the FLL is heavily duty-cycled and turned on only to calibrate a lower-frequency oscillator to compensate its drift due to noise and environmental changes, thus achieving ultra-low-power dissipation. This thesis explores the design and implementation of the first LC-based FLL by proposing a system architecture, analyzing its limitations and proposing a transistor-level implementation. The resulting time reference, when implemented in TSMC 40-nm process, consumes 773.29𝜇𝑊 power and achieved an estimated 41.89𝑝𝑝𝑚/ 𝑜𝐶 temperature coefficient within an 0.389𝑚𝑚2 chip area.

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network learning algorithms. However, as edge platforms are increasingly multi-core, new techniques are required to deploy learning algorithms on multi-core designs.
In this report, the performance of a low-cost multi-core on-chip learning platform with the local error learning (LEL) algorithm is evaluated. First, we reviewed state-of-art learning algorithms designed to solve the challenges of efficient neural network learning. We analyze these algorithms from the point of view of performance, hardware overhead, scalability, and the possibility of multi-core implementation. We propose a spatio-temporal learning framework for the combined use of LEL and e-prop. As a first proof of concept, we aim first at demonstrating multi-core LEL learning for image classification. Next, we constructed a software model suitable for multi-core on-chip driven by hardware requirements. With the software model, we then implemented the corresponding hardware and deployed it on a system-on-chip field programmable gate array (SoC FPGA) board to evaluate the performance. Results based on the CIFAR-10 image classification dataset show that the hardware design can fully reproduce the software runtime results. With a classification accuracy of 59.57\% after batch-size-1 on-chip learning, our design forms a stepping stone for the development of low-cost multi-core hardware that can adapt online to its environment.

The growing interest in edge computing is driving the demand for more efficient deep learning models that fit into resource-constrained edge devices like Internet-of-Things (IoT) sensors. The challenging limitations of these devices in terms of size and power has given rise to the field of tinyML, focusing on enabling low-cost machine learning on edge devices. Up until recently, the work in this space was primarily focused on static inference scenarios. However, a prominent issue with this is that models cannot adapt post-deployment, leading to robustness issues with shifting data distributions or the introduction of new features in the data. However, at the edge, full on-device retraining, or communicating all new data to a central server, is infeasible: this necessitates the development of data-efficient learning algorithms to adapt locally and autonomously from streaming data. This challenge at the intersection of edge computing and data-efficient learning is currently an open challenge.
In this thesis, we propose to solve this challenge with meta-learning. To clarify in which way the application of meta-learning is the most suitable for edge hardware, for the first time, a principled approach for meta-learning at the edge is outlined and investigated in three parts.
The first part of this thesis details the selection of a suitable neural network architecture for few-shot learning over sequential data. By not being fixated on one architecture from the start, it is possible to explore different approaches to learning over sequences of temporal data, leading to the identification of the most effective architecture for generalizing from limited temporal examples. The quantitatively evaluated architectures are a recurrent neural network (RNN), a gated recurrent unit (GRU), a long-short-term memory (LSTM) and a temporal convolutional network (TCN). We show that TCNs outperform all architectures, while GRUs and LSTMs have a lower activation memory requirement. However, the latter require a linearly increasing number of multiplications with input sequence length, while it scales logarithmically for TCNs. Our results show that TCNs therefore provide the most favorable trade-off for low-cost temporal feature extraction at the edge.
The second part of the thesis focuses on the algorithmic developments of the few-shot learning setup. Building on recent results from machine learning research, we highlight how meta-learning techniques primarily rely on learning high-quality features that generalize well. Taking into account hardware-driven considerations such as memory and compute overheads and through detailed quantitative analyses, we demonstrate that the best performance-cost trade-off is reached with a simple supervised pre-training scheme, where on-chip learning is performed by comparing the outputs of a TCN-based feature extractor with Manhattan distance. We also analyze the impact of quantization on this trade-off and, accordingly, we select a scheme with 4-bit logarithmic weights and 4-bit unsigned activations...

Switched-capacitor power converters (SCPCs) have emerged as promising alternatives to traditional inductive power converters due to their CMOS integration capability and configurable conversion ratios. However, challenges such as output ripple, power efficiency, and transient response have hindered their widespread adoption. This article presents a novel Hybrid Hysteresis-CFM (HHC) control strategy that effectively addresses these issues.

The HHC strategy combines the best of both worlds, integrating hysteresis control and Continuous Frequency Modulation (CFM) control. During transient moments, the system utilizes a coarse/fine frequency tuning approach to rapidly reach the target frequency. Simultaneously, hysteresis control ensures that overshoot and undershoot are kept within predefined limits, significantly reducing output ripple during load transitions.

To enhance performance and versatility, the proposed system employs a Recursive Switched Capacitor (RSC) topology with adaptive capacitor sizing and 10-phase time-interleaving. This configuration enables configurable voltage-conversion ratios (VCRs) and high power conversion efficiency (PCE) across a wide input-output range.

Experimental results validate the effectiveness of the HHC SCPC. It demonstrates minimal overshoot and undershoot during load transition, maintains a low output voltage ripple during steady-state operation, and achieves high PCE. Comparative analysis with state-of-the-art DC-DC converters underscores the superior performance of the proposed system.

In summary, the Hybrid Hysteresis-CFM (HHC) control strategy offers a promising solution to enhance the capabilities of switched-capacitor power converters. Its ability to address output ripple, power efficiency, and transient response challenges makes it a valuable innovation for diverse applications requiring efficient power conversion.

Spiking neural networks (SNNs), which are regarded as the third generation of neural networks, have attracted significant attention due to their promising applications in various scenarios. Based on SNNs, neuromorphic coprocessors, designed to emulate the structure and functionality of biological brains, hold the potential to revolutionize computing. However, these coprocessors encounter challenges related to adaptability and flexibility in various application environments once they are manufactured. To tackle this challenge, our project introduces a neuromorphic System-on-Chip (SoC), which seamlessly integrates a RISC-V CPU with an SNN coprocessor, utilizing sparse time-to-first-spike encoding (TTFS). The primary goal of this SoC is to facilitate the complete reconfigurability of the SNN coprocessor with the RISC-V CPU. By leveraging this neuromorphic SoC and successfully simulating the novel loop learning work model to achieve an accuracy of 92.2\% on the MNIST dataset, we demonstrate its capability to adapt the SNN coprocessor for various application scenarios, such as text recognition and face detection.

With the introduction of event-based cameras, such as the dynamic vision sensor (DVS), new opportunities have arisen for low-latency real-time visual data processing. Unlike traditional frame-based cameras that capture entire frames at fixed intervals, each pixel in an event-based camera operates asynchronously, generating an event whenever its brightness change exceeds a certain threshold. Although DVS sensors inherently surpass traditional frame-based cameras in capturing transient, high-speed phenomena, their performance bottleneck is usually located in their address event representation (AER) readout interfaces. The commonly used row-scanning synchronous AER, which encodes events in a full row at once, offers high throughput. However, this approach also introduces inherent delays that limit its use in applications requiring high temporal resolution. Conversely, while AER schemes based on asynchronous digital circuits surpass synchronous schemes in temporal resolution, their event-by-event transmission approach limits their overall throughput.

This work proposes a novel high-speed asynchronous AER interface, leveraging spatiotemporal correlations in DVS event-based data, to optimize the tradeoff between temporal resolution and throughput. Supported by the recently proposed open-source asynchronous design toolkit (ACT) flow for asynchronous digital circuits, we propose an address fuser to be integrated into the hierarchical token ring (HTR) AER scheme. This address fuser creates a spatiotemporal window to exploit the inherent spatiotemporal correlations in DVS data. After verification at both switch- and transistor-level simulations, we benchmarked our design against the conventional HTR AER scheme using a representative set of input scenarios. Our design achieved 196% of the throughput for multi-event transmissions when all pixels were activated simultaneously, at the expense of an acceptable 18% latency increase for single-event transmissions with a 10-ns temporal window.

Recent trends in machine learning (ML) have placed a strong emphasis on power- and resource-efficient neural networks, as well as the development of neural networks on edge devices. Spiking neural net-works (SNNs), due to their event-based nature, are one of the most promising types of neural networks for low-power applications. To accelerate and ease the deployment of SNNs on edge devices, this thesis presents a configurable digital neuromorphic hardware generator for heterogeneous computing that is capable of generating resource-efficient SNN processing cores. The proposed hardware generator is de-veloped using SpinalHDL, a high-level hardware description language (HDL), which provides a high level of flexibility in hardware generation. Our generator supports the configuration on various parameters and is capable of generating a tree-structured multi-core architecture of heterogeneous cores. The generator is deployed in a sensor-fusion hand-gesture classification use case, for which the configurability of our hardware generator is a key enabler.

In today's highly information-based society, portable smart devices are helping everyone all the time. At the same time, many of them need corresponding power management modules to provide them with stable power from the Li-ion battery. Since different functional modules require different voltage levels, a special DC-DC converter or driver must be designed to meet the requirements. In this thesis, one design is proposed to fulfill the requirement of high efficiency, and another one achieves fully integrated.

This thesis proposes a hybrid DC-DC step-up converter with a new architecture by merging a traditional inductor-based (IB) boost converter with a switched-capacitor (SC) converter to boost 3-4.2-V input to 20-30-V output. By serially connecting an IB boost converter and a 1:6 Dickson SC converter, the capacitors take over most of the output voltage stress. As a result, the voltage stress over each switch is limited to 5 V, which makes it possible to implement all the power switches with only on-chip 5-V devices. Thanks to the 5-V devices, the overall power conversion efficiency is improved in various aspects. The switching frequency of the SC stage is decreased by the soft charging technique, which helps further improve the efficiency. The proposed converter is designed and simulated in TSMC 0.18 um BCD process. An efficiency of 93.08 % is achieved under 3.7-V input and 29-V output voltage with a 25-mA current load.

A fully integrated VCSEL driver with adjustable pulse width is also proposed in this thesis. By combining two separate control signals, the VCSEL driver is able to overcome challenges posed by PVT and technology process limitations to achieve the narrowest pulse width of around 300-ps. The proposed converter is designed and simulated in SMIC 55 BCD process.

This article presents a novel wide operational range reconfigurable regulating rectifier for wireless power transfer. The proposed 1X/2X/3X rectifier achieves wide range voltage regulation without global loop control to minimize the area occupation. Compared with previous work, more working modes and greater magnification allow the proposed rectifier to regulate smaller signal, which extends voltage regulation range. A novel local loop control system is proposed for voltage rectification with three modes. The local loop adaptively senses the duty cycle of mode signal to determine which two working modes the rectifier should work with and configure the rectifier in these two modes. Then the rectifier are switching between two working modes according to the comparison result with reference voltage. Also, the change of which two working modes are also triggered by a window comparator to make sure the change happens when the output voltage is far away from reference voltage. The system is designed and simulated in a 0.18um BCD technology. The measurement results show that the proposed system can rectify wide-range input AC power to a regulated output. The achieved voltage conversion ratio (VCR) is 0.95-2.68 with a peak power conversion efficiency (PCE) of 87.4%.

With the high-speed development of the Internet of Things (IoT), powering such a massive number of wireless IoT sensors with chemical batteries become more and more unpractical. To make the IoT sensors self-sustained, Piezoelectric Energy Harvesting (PEH) technology provides an excellent solution to power the devices with a relatively long service time. By harvesting the ambient mechanical vibrations, PEH could generate a stable power source without wind or light.

Currently, the famous bearing manufacturer, SKF, collaborates with TU Delft to design a self-sustained smart IoT roller with PEH technology, which will be implanted in huge bearings, such as the bearing in the wind turbines. This thesis project is a feasibility study investigating the possibility of replacing the chemical battery with the Piezoelectric Energy Harvester in SKF's smart IoT roller, called Sensor Roller.

The objective of this project includes the system design of two generations of the prototype harvester. The first prototype concentrates on the properties of the piezoelectric material, while the second prototype focuses on the structure of the harvester. The design work consists of the raw data analysis of the target roller from SKF and the prototype construction and simulation in COMSOL Multiphysics. Besides, to make the results more reliable, two stages of the test with the practical components are made to study the harvester's performance under the actual working condition of the roller in the bearing. As a result, a tube shape Piezoelectric Energy Harvester with suitable materials and parameters is built. According to the simulation results, under a safe pressure level of the piezoelectric material, the proposed harvester achieves 8.1mW output power, which is enough for the loading sensors. The designed Piezoelectric Energy Harvester is being manufactured at present, and it is planned to be installed in the target roller to get the system-level test in the future.

In addition to the harvester, some rectifiers are designed and taped out to improve the performance of the proposed Piezoelectric Energy Harvesting system. Three rectifiers are made with the Silicon Carbide (SiC) process to obtain a high voltage and temperature tolerance: a Full Bridge Rectifier (FBR), a Passive Rectifier, and a Synchronized Switch Harvesting on Inductor (SSHI) rectifier. Meanwhile, another SSHI rectifier is made with the 0.18um Silicon BCD process that focuses on solving the cold-startup problem. Consequently, simulated with the real transducer of the proposed harvester, both the FBR circuit and the Passive Rectifier circuit with the SiC process achieve over 10mW output power, and the SiC SSHI circuit achieves 37.1mW output power. As for the cold-startup SSHI rectifier circuit, it successfully reduces the required open circuit voltage by 4x to start up the SSHI system from the cold state.

The results of this project show the great potential for applying the Piezoelectric Energy Harvesting technology to power the IoT sensors in the roller of bearing. Although some future works should be finished to build the commercial version of the energy harvesting roller, we are convinced that the fully self-sustained Sensor Roller with Piezoelectric Energy Harvesting technology will possibly show up in the near future.

The current generation of power management integrated circuits require fully integrated, low cost and low power solutions for voltage regulation. As final blocks in the internal power supply chain, excellent performance linear voltage regulators are required, especially in terms of dynamic response and stability. Since many voltage regulators are used, the chip area consumed by the regulators is a point of attention. Additionally, for some internal voltages the load current or capacitive loading is much lower, such that a scalable compact solution would be preferred. This project focuses on minimizing the on-chip area of voltage regulators while maximizing their performance.

The proposed design incorporates a novel circuit technique for improving the dynamic response of linear voltage regulators. In this thesis, the theory and analysis of current amplifier-based NMOST linear voltage regulators is introduced. In order to maximize the dynamic performance, multiple implementations are analyzed and their drawbacks are presented. Adaptive biasing has been implemented in order to improve the slew rate at the gate of the pass transistor and to increase the voltage loop gain bandwidth. The current loop is stabilized by means of bandwidth enhancement resistors, reaching a unity gain frequency of over 500MHz at maximum load current condition.

The linear voltage regulator occupies an area of 0.0078 mm2, consumes a quiescent current of 8.5µA and has a current capability of 10 mA. The circuit operates at supply levels varying between 7 to 18V, provides an output regulated voltage of 1.8V and is scalable in terms of the load capacitance and the load current. This design achieves a FOM of 0.613ps and is comparable to state-of-the-art designs.

Atrial fibrillation (AF) is the most common type of cardiac arrhythmia occurring in around 0.5% of the world population. AF is characterized by the rapid and irregular beating of the atrial chambers of the heart, which can cause lead to strokes and other heart-failures. To prevent these consequences the early detection of AF is paramount. Using photoplethysmography (PPG) heart activity can be measured from which the inter-beat-interval (IBI), the time between heart beats, can be estimated. Using data collected by a PPG sensor the aim is to classify the heart activity as either AF or Normal Sinus Rhythm in real time using machine learning and collect the outcomes for further analysis by medical professionals. For this a classification method is suggested which is able to be implemented on an ARM based processor. Using a Support Vector Machine and 10 features derived from the IBI's and the PPG signal this algorithm achieves the following accuracy metrics: balanced accuracy = 0.853, sensitivity = 0.850, specificity = 0.856 and Matthews Correlation Coefficient (MCC) = 0.643. Compared to similar studies these results are substandard and should be improved.

The accuracy of a true-RMS detector board based on the Analog Devices LTC5596 is determined by measuring the input power and the output voltage. A number of samples of the output voltage is taken and the mean and standard deviation is shown. These measurements are done for single-tone excitation with a direct connection and over-the-air setup, and for multi-tone excitation with a direct connection.

It has been demonstrated that the detector response worsens with over-the-air excitation, resulting in a doubling of the standard deviation in the output voltage compared to a direct connection. With multi-tone excitation, the standard deviation is fifteen times higher than with a direct connection. Additionally, with multi-tone excitation the mean output voltage is lower than with the same input power as single-tone. This discrepancy increases with the amount of tones.

A Keysight Advanced Design System simulation is also presented for the three different measurement setups. With the use of a Monte Carlo simulation uncertainty bounds between the function generator and the power detector are made. Furthermore the noise of the power detector is simulated and sources of noise analyzed.

The ΔΣ analog-to-digital converter (ADC) is widely used in audio applications for its high resolution. However, it is less energy efficient compared to Nyquist Rate ADCs. The growing demand for portable and wearable devices poses a more stringent power-efficient requirement on the audio system, and the traditional ADCs architecture is hard to achieve both high linearity and high energy efficiency. Zoom ADC is a proven energy-efficient hybrid structure for high-resolution and high-linearity applications. It consists of a front-end successive approximation register (SAR) ADC as a coarse stage and ΔΣ modulator backend to take advantage of the energy efficiency of a SAR ADC and the high resolution of a ΔΣ. However, the conventional zoom ADC suffers from distortion due to the input-correlated quantization error from the coarse stage. The tonal behavior (also known as “fuzz”) degrades overall linearity. This thesis describes a low cost, calibration-free method to suppress the fuzz in the zoom ADC. It improves the SNDR by introducing a 1st order fully passive noise shaper with a dithering to the coarse SAR ADC, which reduces the correlation of its quantization error with the input. A prototype ADC has been implemented in standard 160 nm CMOS process. It achieves 104.4dB peak SNR, 103.8 dB SNDR and 106.5 dB dynamic range (DR) in the audio band (20Hz~20kHz) at an oversampling ratio (OSR) of 62.5. The ADC consumes 317 μW from a 1.8V supply, thus resulting in a Schreier FoM of 185 dB.

Class-D amplifiers are widely used in automotive audio systems because of their high efficiency. In modern car sound systems, multiple amplifiers are used to provide good audio effect. However, typical class-D amplifiers have a high idle-power, which can drain the battery quickly. To solve this problem, an ultra-low idle power class-D amplifier is proposed in this thesis. The simulation results show that this amplifier can achieve very low idle power while maintaining competitive linearity and efficiency.

This work describes a low-power and low-cost alternative to mechanical wind sensors, suitable for volume production in standard CMOS processes. The CMOS wind sensor operates in the electro-thermal domain; therefore, it has no moving parts and therefore requires very little maintenance. Moreover, the CMOS wind sensor is an active sensor, compared to its mechanical counterpart. Its sensitivity can be easily adjusted by changing the magnitude of the excitation signal.

Despite the manufacturing advantages of CMOS technology, the wind sensor has not attained commercial success in the market. This is due, in part, to process spread and packaging artifacts that have resulted in offset, nonlinearity and angle errors in detecting wind speed and direction. Because of this, expensive manual calibration is required to compensate these errors. Furthermore, its power consumption, in the order of tens of milliwatts, is not yet low enough to compete with its MEMS counterparts.

In this thesis, the design of a new version of the wind sensor is described, which aims to address the drawbacks of previous designs. Four extra resistors were added at each corner to electrically compensate for packaging artifacts, with the aim of reducing calibration costs. Larger thermopiles (a number of thermo- couples in series) were used, resulting in a greater signal-to-noise ratio (SNR). Internal signals were buffered to output pads to gain more insight into the magnitude of the sensor's internal signal swings. With these improvements, the resulting wind sensor chip consumes less than 30 mW of heating power and has an accuracy of ±0.6 m/s (speed) for wind speeds ranging from 1 to 25 m/s, and ±2.5°(direction) for a range of 4 to 25 m/s.

An oscillator device for generating an oscillator signal, includes a heater arrangement, a first switching element, a temperature sensor, signal process means, and voltage controlled oscillator; an output of the temperature sensor being connected to an input of the signal processing means, and an output of the signal processing means being connected to an input of the voltage controlled oscillator. The first switching element is arranged for receiving the oscillator signal from the voltage controlled oscillator and for providing a heater drive signal to either a first heater element or a second heater element of the heater arrangement based on the oscillator signal. The signal processing means comprise a synchronous demodulator.@en