Low-cost multi-core on-chip learning schemes

Abstract

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network learning algorithms. However, as edge platforms are increasingly multi-core, new techniques are required to deploy learning algorithms on multi-core designs.
In this report, the performance of a low-cost multi-core on-chip learning platform with the local error learning (LEL) algorithm is evaluated. First, we reviewed state-of-art learning algorithms designed to solve the challenges of efficient neural network learning. We analyze these algorithms from the point of view of performance, hardware overhead, scalability, and the possibility of multi-core implementation. We propose a spatio-temporal learning framework for the combined use of LEL and e-prop. As a first proof of concept, we aim first at demonstrating multi-core LEL learning for image classification. Next, we constructed a software model suitable for multi-core on-chip driven by hardware requirements. With the software model, we then implemented the corresponding hardware and deployed it on a system-on-chip field programmable gate array (SoC FPGA) board to evaluate the performance. Results based on the CIFAR-10 image classification dataset show that the hardware design can fully reproduce the software runtime results. With a classification accuracy of 59.57\% after batch-size-1 on-chip learning, our design forms a stepping stone for the development of low-cost multi-core hardware that can adapt online to its environment.