Internet-of-Things (IoT) applications require nanowatt (nW) power references that are robust to process, voltage, and temperature (PVT) variations. This thesis presents the design of ultra-low-power (ULP) sub-10nW always-on blocks in GlobalFoundries 22nm (GF22nm) technology, including a Proportional to Absolute Temperature (PTAT) current reference, a bandgap reference, and a Low Dropout Regulator (LDO). These references are optimized to operate over the full automotive temperature range while consuming only 1nA of current per branch.

Given the high cost of GF22nm technology, achieving area efficiency is a critical aspect of this research. To address this, the design incorporates area-efficient components such as switched capacitors and duty-cycled resistors. The PTAT block achieves a line sensitivity of 2%/V and 5% spread (σ/μ) at 27°C consuming 4nW by utilizing MOSFETs in weak inversion and operates with an 800mV supply voltage while occupying a silicon area of 0.001mm². The bandgap reference is supplied from a battery with an end-of-life (EOL) voltage of 900mV. It achieves a maximum temperature coefficient (TC) of 140.6ppm/°C and a line sensitivity of 0.56%/V at 27°C with a supply range from 900mV to 1.98V. Without resistor trimming, the reference voltage spread due to process and mismatch variations is reduced to 2.9% (σ/μ) by using BJTs. The bandgap reference occupies a silicon area of 0.021mm² using duty-cycled resistors and has a nominal power consumption of 7.6nW. This voltage is used as the reference voltage for an LDO with unity-gain feedback to prevent multiplication of the reference voltage noise. The LDO maintains an output voltage line sensitivity of less than 1%/V with battery voltage variations from 900mV to 1.98V and load currents ranging from 100nA to 1µA.

CMOS Hall sensors consist of current-biased n-well plates that output magnetic-field dependent voltages. Offsets due to n-well inhomogeneity can then be suppressed by the spinning-current technique, which involves periodically rotating the direction of the biasing current and averaging the resulting output voltages. However, its effectiveness is limited by the JFET effect, which refers to the formation of a depletion region between the n-well and the p-type substrate due to the voltage drop across the n-well. This depletion region modulates the n-well resistance, and so is also a source of residual offset.

In this work, a CMOS Hall sensor is reported which employs voltage biasing and reads out the short-circuit Hall current. Compared to current biasing, this stabilizes the voltage drop across the n-well and significantly reduces the offset due to the JFET effect. Implemented in a standard 180nm CMOS process, the resulting sensor achieves a 3σ offset of 1.1μT with a noise floor of 60nT/√Hz. Compared to the state-of-the-art, these results represent a 3x reduction in offset, and a 5x improvement in resolution.

This thesis describes the implementation of a phase-domain readout system for a thermal-diffusivity (TD) based temperature sensor. Such sensors measure the phase shift of an electro-thermal filter (ETF), which exhibits a near-linear dependency on absolute temperature. The phase shift is measured by a phase-domain delta-sigma modulator (PD-DSM). Although ETFs can be very accurate, their readout circuitry often constrains overall performance. A notable concern is their offset, which is usually much larger than the ETF’s output signal and may cause the PD-DSM to clip. In this work, this issue is addressed by a hybrid offset-reduction strategy. The PD-DSM itself is designed to achieve a temperature inaccuracy of 0.04°C.
The design was fabricated using TSMC 180nm CMOS technology. Due to a design error, the PD-DSM did not achieve the targeted accuracy. Nonetheless, the hybrid offset cancellation scheme works as intended, demonstrating efficacy by effectively mitigating residual offset to sub-µV levels across temperature ranges extending up to 180°C.

In this thesis, a low-power, high-accuracy BJT-based temperature sensor is proposed, which consists of two main parts: a BJT-based dual-mode front-end (DMFE) and a tracking Delta-Sigma-Modulator (DSM). The front-end employs vertical PNP transistors, which, compared to NPNs, exhibit fewer non-idealities when biased at nA-level currents. The proposed DMFE generates accurate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages, while only consuming half the power of a conventional front-end. The temperature dependent ratio of these voltages is then digitized by an energy-efficient tracking DSM. The prototype sensor was fabricated in a 0.18µm CMOS process and has an active area of 0.228mm2. Measurement results show that the sensor achieves an inaccuracy of ±0.15°C (3σ) over the industrial temperature range (-45°C to 85°C) after 1-point temperature calibration, which corresponds to a relative inaccuracy of 0.3%. It also achieves a 32mK resolution in 100ms, while consuming only 130nW. Its low power consumption, accuracy, and resolution make it suitable for IoT applications.

This thesis describes the design, implementation, and characterization of integrated RC frequency references. The primary focus of the work is a frequency-locked loop (FLL) architecture, realized in standard CMOS, that digitizes the phase shift of an integrated RC filter, processes the results in the digital domain, and uses it to control an output frequency to maintain its accuracy over temperature variations.....@en

This thesis describes the development of high-performance Class-D audio amplifiers, outlining their significance in modern audio systems. The primary aim is to reduce the system cost and size associated around Class-D amplifiers by minimizing the use of off-chip components, while ensuring high performance and audio fidelity.

Chapter 1 introduces audio amplifiers as integrated circuits, highlighting their role in amplifying electrical signals to drive loudspeakers in various applications. It outlines the key factors influencing amplifier design, including system cost and size, output power, efficiency, electromagnetic interference (EMI), and audio fidelity. The chapter briefly discusses two major classes of amplifiers- Class-AB and Class-D amplifiers (CDAs), particularly emphasizing the latter for high efficiency benefits on account of the switching output stage. Additionally, it introduces the two types of speakers that the amplifiers in this work are optimized to drive, the conventional electrodynamic speaker and the increasingly popular piezoelectric speaker. The discussion includes the advantages and disadvantages of each speaker type and how their electrical impedances impact amplifier design.

Chapter 2 delves into the architectural and circuit techniques used in modern CDAs, comparing different output stage topologies and modulation schemes, and their impact on high-frequency PWM energy and ripple current — key measures of the amplifier’s EMI performance. It introduces conventional AD / BD PWM modulation schemes, highlighting their high frequency PWM characteristics from DM and CM perspectives, before exploring more complicated multi-level and multi-phase architectures that aim to reduce the ripple content and EMI. The trade-offs between these modulation schemes in terms of EMI performance and component requirements are examined. It discusses the benefits of increasing the PWM switching frequency above the AM band ( 1.7MHz), which then allows for smaller and cheaper LC filters. Pulse-density modulation (PDM) using a 1-bit delta-sigma modulator (ΔΣM) is covered, emphasizing its benefits in terms of linearity and challenges related to wideband quantization noise and EMI. Lastly, the chapter also addresses the adaptability of CDAs for driving various speaker loads, particularly newer piezoelectric speakers, and discusses innovative techniques for damping LC resonance without external resistors, significantly reducing power consumption and system cost.

Chapter 3 outlines the development of a 28WCDA for automotive applications, employing a hybrid multibit ΔΣM-PWM scheme to achieve high linearity and low EMI in the AM band. The design features a fully-differential 3rd order loop filter, a multilevel non-uniform quantizer, and an H-bridge output stage that operates at a switching frequency above the AM band. This hybrid modulation technique addresses the limitations of 1-bit delta-sigma modulation, and significantly reducing out-of-band emissions while maintaining high linearity across a broad output power range thanks to the high-gain loop filter. The digital and analog circuits in this design, including the loop filter integrators and quantizer, are designed with low-voltage devices to ensure area and power efficiency. In contrast, the high-power output stage and driving circuits are built with more robust high-voltage devices. This prototype amplifier meets the stringent CISPR-25 EMI standards within the AM band using a relaxed LC filter, while also achieving high linearity, dynamic range, and supply rejection. Chapter 4 introduces a CDA that incorporates a dual voltage/current feedback (VFB/ CFB) topology, specifically designed to drive capacitive piezoelectric speaker loads without the need for external damping resistors. This dual-loop structure effectively mimics a series resistor in an LCR network, allowing for resistor-less LC resonance damping, thereby reducing cost, size, and power consumption. Load current sensing, used in the CFB path, is implemented using purely low-side on-chip sense resistors, thereby avoiding high-frequency switching issues and simplifying the readout network. This low-side sensing is feasible due to the push-pull modulation scheme, which is advantageous for a low-power design. Techniques such as CFB filtering and chopping are employed to reduce non-idealities like noise and non-linearity in the feedback paths. The prototype, fabricated in a 180 nm BCD process, can drive a 4 μF load with a peak current of 4.4 A and achieves an idle power consumption of 122 mW. Measurement results confirm the system’s efficacy in damping LC resonance and maintaining high performance, with significant power savings compared to traditional designs using external resistors.

Chapter 5 builds upon the dual feedback architecture introduced in Chapter 4 by incorporating a quadrature chopping scheme to further enhance the linearity and noise performance of Class-D amplifiers. This technique addresses timing skew issues between low-voltage input choppers and high-voltage output choppers, which can degrade signal linearity and increase noise. The quadrature chopping scheme dynamically matches the timing of the choppers, resulting in significant improvements in large-signal total harmonic distortion (THD) and a reduction in noise foldback into the audio band. The chapter presents measurement results that demonstrate the extension in the linear output of the amplifier to close to 95% the full-scale.

Chapter 6 concludes the thesis by summarizing the key findings and contributions of the research. It highlights the original contributions, including the hybrid PWM-DSM modulation scheme, the dual feedback topology for resistor-less damping of capacitive piezoelectric speaker loads, and the quadrature chopping scheme for further improved linearity and noise performance. The chapter also discusses potential future research directions, such as further optimization of EMI performance through advanced modulation techniques, improved current sensing methods, and enhanced feedback accuracy.
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Temperature greatly affects the performance of integrated circuits, and so temperature sensors are often necessary to ensure reliable operation and stable performance. The goal of the work described in this thesis is to realize a temperature sensor in CMOS technology that can be produced at low cost. In the first step, a temperature sensor is developed that, unlike its predecessors, does not require individual batch calibration, thus significantly reducing calibration costs. In the second step, low-cost calibration methods are developed to calibrate the sensor at two different temperatures: room temperature and an elevated temperature created by an on-chip heater. These calibration methods are used to correct the shifts in the sensor's output caused by the mechanical stress of plastic packaging or to maintain the sensor's accuracy over a wide temperature range. In the final step, additional functionality is added to the sensor to measure external capacitances and voltages. This is achieved by reusing the circuitry of the temperature sensor, thereby making a cost-effective use of its area.@en

Advanced Systems-on-Chip (SoCs) exhibit significant self-heating and require thermal management to prevent overheating. Sensors for this application should be not only small so that they can be placed ubiquitously, but they should also achieve moderate accuracy and resolution within 1 ms so that the die temperature can be monitored with approximately 1°C of measurement error. BJTs are the traditional elements that are used to sense temperature, but they require large headroom and are difficult to miniaturize. Thermal diffusivity relies solely on lithography for its accuracy and is easy to miniaturize, but it requires a significant amount of power (a few mWs) to generate the local heat pulses that it uses to measure temperature. MOS-based temperature sensors do not require the headroom that BJT-based sensors do, but they do require a large area to minimize the effect of aging and drift. Resistors achieve superior energy efficiency, moderate accuracy (enough for thermal management), and have no headroom requirements. However, at the beginning of this work, these types of sensors were not yet miniaturized. @en

CMOS amplifiers suffer from offset (several mVs), offset drift (several µV/°C) and 1/f noise corner (tens of kHz). Dynamic offset compensation (DOC) techniques, such as auto-zeroing and chopping, are often used to achieve low offset (µV level), offset drift (< 20 nV/°C) and 1/f noise corners (several Hz). However, these techniques also have drawbacks, mainly due to the required input switching. This results in unwanted spikes, input current and intermodulation distortion. This thesis presents DOC amplifiers with sub-pA input current, low distortion, as well as quiet outputs.@en

Event-based cameras promise new opportunities for smart vision systems deployed at the edge. Contrary to their conventional frame-based counterparts, event-based cameras generate temporal light intensity changes as events on a per-pixel basis, enabling ultra-low latency with microsecond-scale temporal resolution, low power consumption at milliwatts level, and sparse information encoding where only dynamic objects trigger events, effectively excluding static background data. However, mainstream computer vision algorithms based on convolutional neural networks (CNNs) hardly exploit these advantages of event-based cameras. Recently, event graph neural networks (event-GNNs) have been proposed as the backbone for novel event-based vision algorithms. By treating events as graph data, GNNs are able to process events while preserving their spatiotemporal information and sparse characteristics. Further studies also revealed an event-driven computation workflow that translates an event stream into a dynamic, evolving graph, outlining a path toward low-latency event-based vision. Despite these promises, event-GNNs are still calling for dedicated hardware accelerators toward integrated solutions with real-time prediction latency and low power consumption for real-world edge intelligence.

In this thesis, for the first time, we proposed an event-driven GNN accelerator for low-power, high-speed edge vision. Through hardware-algorithm co-design, an event-driven GNN model is adopted for deployment on an edge FPGA platform without prediction accuracy loss. We also pointed out two novel optimizations, edge-free storage and layer-parallel computation, to further decrease memory footprints and processing latency. The proposed accelerator is implemented on the Xilinx KV260 System-On-Module (SOM) platform containing an UltraScale+ MPSoC FPGA, and benchmarked on-board. Targeting a car recognition task based on the NCars dataset, our accelerator achieves a prediction accuracy of 87.8%. Meanwhile, operating with a 6.86W board-level system power, the accelerator reaches an average 16μs prediction latency per event and runs 9.2× faster than its software counterpart running on an NVIDIA RTX A6000 GPU platform. Therefore, our event-driven GNN accelerator efficiently allows for both real-time and microsecond-resolution event-based vision at the edge.

Flow sensing is essential in various industrial, commercial, and biomedical applications. Although many types of flow sensors exist, thermal flow sensors are widely used due to their simple sensing elements (heaters and temperature sensors) and low fabrication costs. A low-cost interface for thermal flow sensors can then be realized with a Thermal Sigma-Delta Modulator (TΣΔM), which regulates the temperature of the sensing element, while simultaneously digitizing the required power.
This thesis discusses the design of a pseudo-differential TΣΔM to read out a thermal flow sensor, which consists of two heating resistors in thermal contact with the flow. The modulator maintains both resistors at a constant temperature and digitizes the required differential power. The resistors have a Positive Temperature Coefficient (PTC) and can thus be used as heaters and temperature sensors in a time-multiplexed manner, resulting in a compact realization. A prototype was fabricated using discrete components on a PCB. With a sampling frequency of 5kHz, the modulator achieved a thermal noise-limited resolution of greater than 13 bits in a bandwidth of 1.5Hz for a full-scale input of 7mL/min. The entire read-out was realized with two integrators, two clocked comparators, and a few switches, resulting in a simple, low-cost interface with direct digital read-out.

This thesis describes the design and simulation of a capacitively-coupled autozeroed and chopped operational amplifier in the TSMC high-voltage BCD 0.18 μm 5 V technology. It uses chopping and autozeroing to achieve high precision (10 μV offset and 50 nV/√Hz noise density) and a capacitively-coupled input stage to safely handle beyond-the-rails 50 V input voltages. The amplifier employs a pseudo-continuous time architecture that periodically autozeroes a single signal path, which is also chopped. Compared to amplifiers with ripple-reduction loops, this approach should potentially result in area and power savings. However, it also means that the signal path is periodically broken during a short deadtime, during which the signal path is autozeroed. Since the presence of the deadtime comes with a noise penalty, the amplifier’s clocking scheme has been optimized to reduce the length of the deadtime relative to the length of the two amplification phases. The simulated performance of the resulting amplifier is comparable with that of other precision amplifiers, while its chip area should be lower, resulting in lower production costs.

This work presents an analog front-end (AFE) signal processing chain for automotive FMCW LiDAR. The AFE consists of a high-gain transimpedance amplifier (TIA) followed by a gain-stage. The gain of the AFE is 103.2dBΩ at a bandwidth of 505MHz. Since the noise of FMCW-LiDAR systems is dominated by the shot noise of the local oscillator (LO), the AFE is noise matched to the optical system. It has an input-referred noise of 13pA/√Hz which is lower than the 16pA/√Hz generated by the optical system. The signal chain is designed to amplify the small single-ended photo current and convert it into a differential output voltage between 7mVpk and 125mVpk that is adequate for digitisation by an ADC. An SFDR=46.4dB is maintained to mitigate the generation of spurious tones, which will cause false object detections. The AFE circuits are sufficiently linear to ensure that such tones are below the noise floor. The signal path is AC-coupled to ensure that the balanced photodetector does not compromise the bias currents of the input stage. An external coupling capacitor defines a 1MHz high pass corner. The AFE was implemented in 0.13μm CMOS technology and occupies 1160μm x 585μm including all supporting circuitry. With a 1.5V power supply, the total power dissipation is 250mW including the ADC-driver. The project was finalised by integrating the AFE with an ADC and the required support circuitry into a full ASIC for use as a building block in LiDAR systems.

This thesis presents the design of a low-power, sub-1V, BJT-based temperature sensor. It is based on a capacitively-biased (CB) BJT front-end, in which capacitors are discharged across diode-connected BJTs to obtain proportional-to-temperature (PTAT) and complementary-to-temperature (CTAT) voltages. These voltages are then digitised by a switched-capacitor Delta-Sigma Modulator (DSM), which employs energy-efficient inverter-based amplifiers that can operate from a sub-1V supply. To mitigate the effects of component mismatch and 1/f noise, dynamic error-cancellation techniques such as chopping, auto-zeroing and dynamic element matching are used in both the front-end and the DSM. After a 1-point temperature calibration, the sensor achieves a simulated inaccuracy of ±0.20oC (3σ) over temperatures ranging from -55oC to 125oC. From simulations, it does this while operating from a 0.9V supply and dissipating only 270nW. It occupies an estimated area of 0.09mm2 in a 180nm CMOS process. Compared to previous CB temperature sensors, this design occupies 2.8x smaller area and dissipates 3x less power.

This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves state-of-the-art energy efficiency. Realized in a standard TSMC 65nm CMOS technology, the modulator achieves 99.24dB SNR, 99.2dB SNDR and 100dB DR in a bandwidth of 24kHz while consuming only 80μW. This translates into the highest energy efficiency (FoMSNDR, 184dB) reported for a continuous-time delta-sigma modulator.

Several techniques have been proposed to reduce the swing at the input stage of a CTDSM. One of these is using a simple passive RC input stage. In prior works, this increased in-band quantization noise. In this paper, we use positive feedback to realize complex-conjugate poles with a passive input stage, obtaining the same noise-shaping as an Active-RC-based loop filter. The prototype 16nm chip achieves a peak SNDR=97.6dB and DR=99.5dB with an SNDR FOM=181.2dB and DR FOM=183.0dB in 20kHz bandwidth.

To be able to cope with the demands of next generation radar applications, a bandwidth of 400MHz is required. The SAR assisted CT ∆Σ ADC provides an energy efficient ADC, but needs improvements to cope with the bandwidth enlargement. This thesis examines the front end components and thus initially focuses on resolving the issues in the front end. Although bandwidth enlargement is possible, the APF limits the performance resulting in an inefficient two-stage architecture. For optimal system efficiency, the APF requirements must be relaxed, which is achieved by decreasing the amount of resolved bits in the coarse ADC. Due to this reduction in bits, more stages must be incorporated into the architecture. To facilitate this, power and error budgets are devised to visualize the effects of adding stages. Hereafter, the 2 bit coarse ADC is compared to a 3 bit coarse ADC. This results in a trade-off
between the applicable gain (APF complexity) and the noise requirements of the front end.
The five-stage (2-2-2-2-6 bit) architecture proves to be the most promising design to achieve the desired FoMs of 172dB. Finally, in an attempt to optimize power efficiency, the APF and LPF filter are revised. The open loop filter implementation is compared to a closed loop filter implementation. It shows
that the open loop implementation exhibits very good power efficiency, but lacks in its linearity.
The closed loop implementation achieves the requirements, but consumes a lot of power. To optimize power consumption, the first and second stage must be implemented with the closed loop filters, but the third and fourth stage must be implemented with the open loop filters.

Due to the precise lithography and highly pure silicon used in IC technology, thermal-diffusivity (TD) temperature sensors can achieve high accuracy without the need for trimming. TD sensors employ electrothermal filters (ETFs) to measure the thermal diffusivity of silicon, i.e. the rate at which heat diffuses through silicon, which is a well-defined function of temperature. This thesis presents two approaches to improve the accuracy and resolution of TD sensors. The first approach investigates the effect of variations in ETF geometry on sensor resolution and proposes a multiplexing scheme to utilize a single readout circuit for reading out multiple ETFs. The second approach aims to investigate the effect of improvements in CMOS technology on sensor accuracy by scaling two ETFs to the 65nm process from the 180nm process. A first-order phase-domain delta-sigma modulator is designed for the readout of the ETFs in the 65nm process, and the previously designed multiplexing scheme is used for cost and time-efficient tape-out. Based on the estimated lithographic error of the 65nm process, the two ETFs are expected to achieve untrimmed inaccuracies of 0.18℃(3𝜎) and 0.36℃(3𝜎), respectively.

This paper presents a 0.01mm2 10MHz FLL-based RC frequency reference that does not require the use of resistors with complementary temperature coefficients (TCs), thus facilitating its implementation in a wide range of standard CMOS processes. Fabricated in a 0.18μm CMOS process, it achieves a frequency inaccuracy of ±0.28% from −45°C to 125°C after a 1-point trim, which is currently the best reported performance for a compact (<0.02mm2) frequency reference.