A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

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This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

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This paper presents a direct conversion transceiver intended for use in a microfluidic NMR flowmeter. It consists of an H-bridge power amplifier, which drives a hand-wound milimeter-sized coil with RF signals, and a direct conversion receiver, which amplifies the NMR signals picked up by the coil, and then digitizes them with an asynchronous 8 bit SAR ADC sampling at 70 MHz. Fabricated in a 65 nm CMOS technology, the receiver achieves a noise spectral density of 1 nV/sqrt(Hz) at 21 MHz, while dissipating only 36 mW. A microfluidic flowmeter based on the transceiver and a handheld 0.5 T permanent magnet can measure flow rates up to 96 ml/h in a 0.8 mm inner-diameter channel with pm 1.3 % full-scale error. To the authors' best knowledge, this is the first reported portable NMR flowmeter.

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Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.

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This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front end uses two resistors to efficiently generate a PTAT and CTAT current, whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. A β-compensation technique is used to mitigate base current errors associated with the NPN's finite β. Component mismatch and 1/f noise are mitigated by applying chopping and dynamic element matching (DEM), while the spread in V_BE and the ratio of the two resistors are digitally trimmed at room temperature (RT). Fabricated in a 0.18-μ m CMOS process, the sensor draws 2.5μ A from a supply voltage ranging from 1.4 to 2.2 V. Measurements on 40 samples show that it achieves an inaccuracy of ± 0.1° C (3Σ ) from - 55° C to 125° C. Furthermore, it is both highly energy efficient, with a resolution figure of merit (FoM) of 200fJċK² , as well as very compact, occupying only 0.07 mm2.

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Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

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Advances in CMOS technologies have led to the development of continuous-time ΔΣ modulators (CTDSMs) with GHz sampling rates that achieve better than-100dBc linearity and bandwidths above 100MHz. However, at low frequencies (below 10MHz), their SNDR is limited by 1/f noise, which limits their use in radio receivers intended to cover both the AM and the FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while maintaining interferer robustness, noise, spurious, and linearity performance. Implemented in a CTDSM sampling at 6GHz, it reduces its 1/f noise corner frequency by 22x and achieves -98.3dBc THD, 122dBFS SFDR in 120MHzBW.

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Dual-output regulating rectifier is highly desired in wireless power transfer (WPT) for sub-100mW bioimplants. Such rectifiers perform voltage rectification and dual-output regulation simultaneously, thus avoiding post DC-DC conversions and cascaded power losses [1 –4]. However, the conventional dual-output structure suffers from a low voltage conversion ratio (VCR) (< 1) due to the full bridge rectifier (FBR) topology (Fig. 1), severely limiting the receiver operation when wireless link condition varies [1–2]. In order to extend the operational range without increasing the power demand from the transmitter, [3] presents a charge-pump based dual-output rectifier; however, it uses 10 power transistors (PTs) and 8 off-chip capacitors, degrading the power conversion efficiency (PCE) and increasing the integration cost. Alternatively, the current-mode dual-output rectifier can realize a VCR higher than 1, but the output power is limited to less than 10mW [4], which is insufficient for advanced bioimplants. In this work, a 13. 56MHz single-stage dual-output voltage doubler (DOVD) is proposed to address the above limitations, which employs only two PTs and a fully integrated design. lt can achieve a peak VCR of1.78 and outputs power up to 8lmWwith a 91.8% peak PCE.@en

This paper presents a nano-power high-side shunt-based current sensor (CS) that digitizes the voltage drop across an on-chip (±1A) or a lead-frame (±30A) shunt. A TC-tunable ADC reference compensates for the shunts' large temperature coefficient (TC), resulting in ±0.5% gain error from -40 to 85°C. The CS employs a capacitively coupled gm-boosted front-end followed by a CCO-based Δ Σ ADC. Together with a floating input chopper, this results in an input common-mode range (ICMR) of 0-to-15V, the largest reported for a CS implemented in a standard CMOS process. It achieves high energy efficiency (164dB FoM) while consuming only 720nW, representing a 4 × improvement on the state-of-the-art and making this the first ever reported sub-μ W smart current sensor.

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BJT-based temperature sensors are widely used due to their high accuracy over a wide temperature range with a low-cost 1-point trim. Although resistor-based sensors can achieve better energy efficiency, they typically require a 2-point trim to achieve comparable accuracy, while thermal-diffusivity based sensors achieve superior accuracy at the cost of energy efficiency [1]. This paper presents a BJT-based temperature sensor that achieves both excellent accuracy and energy efficiency. To avoid the kTfC noise limitations of conventional discrete-time (OT) readout schemes [2], [3], it employs a compact continuous-time (CT) front-end. Component mismatch, which often limits the accuracy of CT front-ends [4], [5], is mitigated by a combination of dynamic element matching (OEM) and a low-cost resistor-ratio self-calibration scheme. As a result, the sensor achieves a resolution FoM of 0.85textpJcdotK 2, and a competitive inaccuracy of pm 0.1 circC (3sigma) from -55 circC tO 125 circC after a 1-point trim. This makes it 4times more energy-efficient than state-of-the-art BJT-based sensors with similar accuracy [2], [4], [5].

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Synchronized bias-flip rectifiers, such as synchronized switch harvesting on inductor (SSHI) rectifiers, are widely used for piezoelectric energy harvesting (PEH) [1], which can replace the use of batteries in many loT applications, thus reducing both system volume and maintenance cost. However, the output power extracted by such rectifiers strongly depends on the impedance matching between the piezoelectric transducer (PT) and the circuit. To maximize this, two maximum power point tracking (MPPT) algorithms are often used. As shown in Fig. 30.3.1 (left), the Perturb & Observe (P&O) (a.k.a. hill-climbing) algorithm adjusts the rectified output power in a stepwise manner towards the maximum power point (MPP), thus establishing robust and continuous MPPT. However, accurately sensing the rectified output power often requires complex and power-hungry hardware [1], [2]. Another simpler algorithm is based on the fractional open-circuit voltage (FOCV) and involves periodically measuring the PT's open-circuit voltage amplitude (VOC) and regulating the rectified voltage (VREC) to a level (VMPP), which corresponds to the MPP [3-6]. However, the PT must be periodically disconnected from the rectifier to measure VOC, resulting in wasted energy, while the inherent delay in sensing VOC variations reduces the overall tracking efficiency. Furthermore, a calibration step is usually necessary to determine VMPP, since this depends on the actual PT voltage flip efficiency (etaF) of the bias-flip rectifier.

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In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is mainly due to finite amplifier bandwidth, which causes signal-dependent output spikes at the chopping transitions. Such chopper-induced IMD can be mitigated by the fill-in technique, which involves ping-ponging between the outputs of two identical OTAs chopped in quadrature, thus generating a spike-free output. In this letter, a relaxed implementation is proposed in which the output of a fill-in OTA is only briefly used to avoid the spikes of a chopped main OTA. As a result, the fill-in OTA does not need to be chopped, and so it can be duty-cycled to save power. Furthermore, the chopper ripple caused by the main OTA can now be suppressed by a single low-noise ripple-reduction loop, rather than the two AZ loops required in a previous ping-pong implementation of the fill-in technique. Compared to the latter, the proposed amplifier achieves similar IMD performance (-125.7 dB), a 25× lower input current (22.6 pA), and a flat noise floor (12 nV/ Hz).

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This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on- chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional- to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from-40 °C to 80 °C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 4.6 mm2 and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only ±2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.

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This article presents a sub-1 V bipolar junction transistor (BJT)-based temperature sensor that achieves both high accuracy and high energy efficiency. To avoid the extra headroom required by conventional current sources, the sensor’s diode-connected BJTs are biased by precharging sampling capacitors to the supply voltage and then discharging them through the BJTs. This capacitive biasing technique requires little headroom ( ∼ 150 mV), and simultaneously samples the BJTs’ base–emitter voltages. The latter are then applied to a switched-capacitor (SC) ΔΣ ADC to generate a digital representation of temperature. For robust sub-1 V operation and high energy efficiency, the ADC employs auto-zeroed inverter-based integrators. Fabricated in a standard 0.18- μ m CMOS process, the sensor occupies 0.25 mm 2 and consumes 810 nW from a 0.95-V supply at room temperature. It achieves an inaccuracy of ± 0.15 ∘ C (3 σ ) from − 55 ∘ C to 125 ∘ C after a 1-point trim, which is at par with the state-of-the-art. It also achieves a resolution figure of merit (FoM) of 0.34 pJ ⋅ K 2 , which is more than 6 × lower than that of state-of-the-art BJT-based sensors with similar accuracy.@en

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.

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CMOS frequency references based on RC oscillators are usually preferred over bulky crystals in loT applications [1-5]. However, due to the process spread and finite temperature coefficient (TC) of most on-chip resistors, RC oscillators require trimming and temperature compensation to achieve decent accuracy. Enabled by high-resolution trimming techniques such as DeltaSigma [1], [2] or pulse-density [3] modulation, recent designs can obtain good accuracy (<0.1 %) at the expense of large chip area. However, existing compact (<0.02mm2) designs suffer from frequency errors in the order of 1% or more [4], [5]. Moreover, their temperature compensation schemes usually require the use of resistors with complementary TCs, which are not available in all CMOS technologies.

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This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors with different TCs. In this work, such a network is used to realize a temperature-dependent reference voltage whose TC cancels that of a single-resistor RC time constant. Compared with the conventional approach, which requires resistors with TCs of opposite polarity, the proposed approach can be implemented with resistors with TCs of similar polarity, and so it can be implemented in most CMOS processes. To compensate for RC spread, a trimmed capacitor is used to adjust the nominal frequency. Two prototype chips were made, one based on p- /n-polysilicon resistors and other based on silicided/p-diffusion resistors. Fabricated in a standard 180-nm CMOS technology, the polysilicon-based prototype has an active area of 0.01 mm2 and an absolute inaccuracy of ±2800 ppm from -45 °C to 125 °C with a fixed TC-trim and a one-point frequency trim. After one week of accelerated aging at 150 °C, however, significant drift (5000 ppm) was observed. The diffusion-based prototype exhibits greater inaccuracy (±14 400 ppm) but much less drift (600 ppm).

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Low-cost metal (e.g., PCB trace) shunts can be used to make accurate current sensors (< 1 % gain error) [1-3]. However, their reported maximum operating temperature (85 circC) is not high enough for automotive applications, and at higher temperatures, shunt resistance may exhibit increased drift, especially at high current levels. This paper presents a metal-shunt-based current sensor with a wide temperature range and a stable on-chip reference current (I textREF) source for shunt self-calibration. By employing a continuous-time (CT) front-end, it achieves an input noise density of 14textnV/sqrttextHz while consuming only 280mu A, making it > 10times more energy efficient than prior art [1], [2], with comparable gain error (pm0.2%) over a wider current (pm 40A) and temperature (-40 circC to 125 circC) range.

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There has been a long-standing interest in controlling and instrumenting the human body. Whether to restore lost function with neural prosthetics, monitor blood glucose levels, or augment human capabilities, there are countless opportunities for sensors inside ( e.g., ingestible, injectable, and implantable) and outside ( e.g., wearable) the body. However, many challenges exist when instrumenting the body. First, many use cases ( e.g., implanted sensors) require long-term recording to capture anomalous behavior—sometimes with limited accessibility—necessitating ultralow power consumption. Second, the power reduction challenge is further exacerbated by size constraints, which limit battery capacity or harvestable energy levels. Third, the signals of interest are often low bandwidth (kHz) and small in amplitude (µV to mV); thus, low-noise front ends are needed. Addressing these challenges has led to a large body of work on the design of highly power-efficient, low-noise amplifiers for biomedical integrated circuits.@en

Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.

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