Emerging, non-volatile memories are promising solutions to contemporary computing problems. These include In-Memory Computing, Neuromorphic Computing, and Machine Learning. We believe that these are not the only possible applications of non-volatile emerging memory devices and that these can be used effectively for tackling several challenges of the ”conventional” computer architecture. For instance, address decoders are an integral part of random access memories. They are typically implemented using fast logic optimised for low latency. They are, however, difficult to test, while their repair is considered to be impossible. In this thesis we research the possibility of a highly scalable and testable address decoder solution, based on Content-Addressable Memories build with ferroelectric transistors (FeFET). This solution can offer numerous advantages including transistor count close to state of the art designs, while outperforming them in terms of latency. In addition, a key advantage could emerge during the testing of this decoder; due to its regular 2D structure, it’s testability is comparable to that of conventional memory arrays. Moreover, it can enable higher production yields, considering that adding a few spare rows will enable end-of-production repair, in the presence of manufacturing defects. By additionally increasing the number of address bits stored in a single FeFET CAM cell, further potential area reductions of 30% - compared to the traditional dynamic NAND decoders - can be achieved.

True Random Number Generators (TRNG) are fundamental cryptographic primitives. They are needed, for example, to generate cryptographic keys and numbers. Poor random number generation can lead to weaknesses in the cryptographic system. A good example can be found in the work of Heninger et al., who managed to retrieve large amounts of private RSA keys due to entropy problems in random number generators used for key generation.

Statistical test suites such as Dieharder and NIST SP 800-22 can be used to determine whether random number generators provide the required entropy. To improve such an evaluation, which is necessary for high-assurance applications, a stochastic model of the noise source must be developed as described, for example, in AIS 20/31.

The research presented in this thesis focuses on designing and validating a noise source based on counting ring oscillator periods. The work presents an analysis of this ring oscillator-based design, consisting of stochastic models, entropy evaluations, high-level and SPICE simulations, and hardware validation using the Intel Arria 10 FPGA platform.

Using the developed models, this work (i) quantifies the improvement in randomness due to sampling the noise source with a second ring oscillator, (ii) establishes a lower bound for the min-entropy of the noise source, and (iii) shows that the design benefits from using ring oscillators with shorter periods and, thus, less area. These findings are verified in high-level and SPICE simulations.

In the end, despite the appealing theoretical benefits of the proposed TRNG noise source, the hardware validation revealed unmodeled noise components, leading to inconclusive results. Consequently, no TRNG implementation based on the designed noise source was made. This highlights the challenges of translating theoretical advantages into successful hardware implementations.

The automotive industry is experiencing a significant shift towards advanced electronic and software integration, driven by the increasing demand for self-driving and autonomous vehicles. With electronics now making up a major portion of vehicle costs, ensuring their reliable operation is critical. However, as the complexity of automotive systems increases, so do the risks associated with malfunctions, requiring a critical need for robust safety measures. Functional Safety (FuSa), as defined by ISO 26262, provides a framework for addressing these concerns at different stages of the safety lifecycle. The primary aim of FuSa is to develop Safety Mechanisms (SM) to detect faults and recover from them. The efficiency of these SMs is indicated by Diagnostic Coverage (DC), which represents the percentage of detected faults. In this context, there are several challenges in verifying the functional safety of automotive chips, especially with RTL designs. For example, identification of safe faults is one of the initial steps in FuSa verification. Discrepancies are observed in their classification when utilising different techniques such as Automatic Test Pattern Generation (ATPG), formal methods and fault injection simulation. This raises questions about the accuracy of overall results obtained from these tools as well. Varying outcomes from fault simulation EDA tools in classifying faults may result in different Automotive Safety Integrity Levels (ASIL) assigned to the component being assessed. This discrepancy would misrepresent the component's ability to reduce associated risks, highlighting the importance of conducting a detailed analysis and comparison of the tools.

The thesis provides a comprehensive evaluation of EDA tools utilized for Functional Safety Verification, focusing on RTL designs. Scripts are developed to automate fault simulation flows of two prominent FuSa EDA tools, XFS by Cadence and VC Z01X by Synopsys, and derive automatic comparisons. By comparing these tools, their strengths and limitations are analyzed. XFS exhibits limitations in fault propagation on input and output ports, resulting in the omission of certain fault scenarios. VC Z01X showcases faster fault simulation capabilities along with an extensive feature set for fault simulation, but lacks support for transient fault injection on a section of the fault subspace. By applying the automated tool flows on a FIFO design enabled with ECC, the DC obtained from XFS and VC Z01X are 68.96% and 80.47% respectively, showcasing a major difference. These findings highlight the importance of a holistic verification methodology that accurately estimates diagnostic coverage.

A novel verification methodology is proposed, which combines the strengths of XFS and VC Z01X to optimize the efficiency and accuracy of fault simulation. Leveraging VC Z01X's concurrent engine for parallel fault injection and XFS's capabilities to cover the unexplored fault space, this integrated approach provides comprehensive fault coverage. The flow also provides users the capability to update fault classification results based on manual analysis or designer inputs, thereby changing the DC as well. The verification methodology is applied to the AutoSoC benchmark suite, an automotive System-on-Chip with configurable SMs. Based on the results, additional SMs are implemented in the AutoSoC design - duplication of pipeline stages with temporal redundancy and ECC on internal memories. This leads to an estimated area increase of 1.4x as compared to the baseline design, but also results in the qualification of an ASIL C level component with a DC of 97.79%. The baseline verification flow included in the benchmark suite provides a DC of 98.36%, which is an over estimation of the actual coverage. The proposed methodology provides a more accurate coverage by taking into account the maximum possible fault space and considering transient faults as well. While there remains room for further improvement in verification methodologies, this framework effectively addresses the fault space required for FuSa verification and provides an accurate estimation of Diagnostic Coverage.

The increasing complexity of Integrated Circuits (ICs) and stringent quality requirements in industries like automotive have contributed to increasing test development time. Virtual testing methodologies, such as AMS-VT, can be used for pre-silicon debugging of test programs, optimizing the test development process. However, AMS-VT has shown limitations in their usage due to the absence of accurate loadboard models, especially in capturing site-to-site variations. To address the lack of an accurate loadboard model for pre-silicon debugging, this research proposes a framework for generating an accurate loadboard model by integrating parasitic effects and possible reflections under real-world conditions.

The proposed framework consists of three main stages. The first stage is an automated netlist generation phase, during which an ideal single-site netlist is created from a multisite loadboard schematic. The ideal netlist is generated considering the AMS-VT environment so that it can be seamlessly integrated into the current virtual testing environment. In the next stage, Cadence PowerSI, which is an Electronic design automation (EDA) tool for parasitic extraction, is automated to extract the parasitics (R, L, G, and C) for all the channels included in the ideal netlist. Finally, in the last stage, a methodology is developed to integrate the parasitics and reflection due to impedance mismatch in the ideal netlist. To improve the accuracy, a static model of the relay was developed that considers its characteristics, such as on-state resistance and off-state current leakage. All these stages are then automated and combined to create a framework that can effectively generate an accurate loadboard netlist that predicts site-to-site variations.

The framework is then validated, with each stage verified independently. The generated ideal single-site netlist was verified against a golden simulation. This verification displayed that the functionality of the generated netlist was accurate and could integrate with AMS-VT seamlessly. The parasitics extracted from PowerSI were validated using a test Printed Circuit Board (PCB) with multiple configurations. This showed that the simulation results using extracted parasitics were within 1% error compared to the IR drop analysis. The relay model was also validated by comparing it with its datasheet, proving that the model accurately considered the physical characteristics. The third stage was then validated by comparing it with PSpice simulations, demonstrating that the model's results were accurate, with the maximum error being below 1.6% for multiple voltages and frequencies. The complete framework was then validated against a physical loadboard, showing maximum errors of less than 2% across all sites and improved timing accuracy for pulse width, reducing it to 0.41% for the proposed framework from 1.6% for the previous methodology. This validation proved that the loadboard generated by the framework accurately modelled parasitics and reflections. The model also accurately accounted for temperature variations, demonstrating its effectiveness in changing operating conditions. By introducing this framework to generate an accurate loadboard model, this research enables a virtual testing environment for faster and more reliable test development, reducing the time-to-market for semiconductor products.

The importance of cybersecurity is ever more increasing. And with that, the importance of anti-tamper technologies. Physical anti-tamper technologies have existed for a while, but passive (battery-less) approaches are lacking. Some solutions exists ([1], [2] and [3]). But are sparse, complex, expensive and only cover a small portion of the device. The subject of this research is that of Glitter Physical Unclonable Function (PUF). A passive physical anti-tamper technology that protects the whole device, and is technology independent. It works as follows:

The secure component (a Printable Circuit Board (PCB)) is placed in an empty box. A camera and Light Emitting Diode (LED)s are added to the center of the PCB. Then a mixture of glitter and transparent resin is poured into the device (including the camera and lights). The resin hardens and the box is closed (being light tight). Enrolment: A picture is taken with the camera inside the box with the LEDs turned on. The light bounces throughout all the glitters. This picture is used to encrypt the critical data on the PCB. When a tamper has occurred (by pruning the enclosure) the glitters are destroyed or irreversibly moved. Thus the picture taken afterwards is different.
Authentication: Another picture is made. If the picture is within a certain threshold (set in enrolment), being the maximum allowed colour distance for each pixel to the reference picture. Then the picture can be used to decrypt the data. Otherwise, access to the data is lost.

For encryption and error correction several algorithms have been researched and tested. Especially the Error Correcting Code (ECC) used in biometrics are interesting, since they have the same criteria as glitter PUF (using real word data as a key); input data not always being the same. For the protoype Fuzzy Commitment is implemented, being the baseline for biometric encryption. A prototype of the glitter PUF has been made using a Raspberry Pi (RPi) camera and a 3D printed case. This prototype is used to evaluate certain characteristics such as how it behaves in time, temperature difference, ageing and what picture settings are most optimal. These
characterizations are important to know how the device behaves when in operation. As they must deviate from the results gathered when an actual tamper has been taken place.

The ageing and temperature tests show that the sytem is susceptible to temperature cycles, but when the same temperature as the enrolment is reached the difference is lessened. Furthermore, the system seems to stabilize and not increase in error after about 23 cycles. After doing so many cycles it can be calculated which (sub)pixels are the most stable. Choosing only the most stable (sub)pixels for enrolment/authentication will reduce the error introduced by temperature and ageing. Drilling shows a linear increase in (sub)pixel distance from the reference. The drill displays hotspots, whereas the temperature tests (mainly) show noise in the red channel. So an algorithm that considers these differences must be implemented. An implementation using binning for error correction, fuzzy commitment, segmenting the picture in small blocks, using Adaptive Equalization; grey-scaling, and taking only 20% of the most stable (sub)pixels, results in 5% of the original picture data while still containing enough information to reliably detect drilling’s.

The security of electronic devices holds the greatest importance in the modern digital era, with one of the emerging challenges being the widespread occurrence of hardware attacks. The aforementioned attacks present a substantial risk to hardware devices, and it is of utmost importance to comprehend the potential detrimental effects they may cause. Side-channel attacks are a class of hardware attacks that exploit information unintentionally leaked by a device during its operation. These leaks manifest in various forms, including power consumption, time variations, and thermal dissipation. The fundamental danger posed by side-channel attacks is their ability to infer sensitive information from these unintended emissions. To address the heightened risks associated with side-channel attacks, this thesis focuses on three main research topics.@en

Internet of Things (IoT) devices regularly process sensitive data, including personal information. Therefore, ensuring their security is crucial to avoid damage and prevent data breaches. The Advanced Encryption Standard (AES) is generally regarded as one of the most popular cryptographic algorithms for ensuring data security. Typical lightweight implementations of the algorithm published in the literature focus on area and power optimization, while neglecting the performance. This paper presents a novel lightweight approach for the AES algorithm and considers both encryption and decryption. In terms of performance per unit area and performance per unit power, our 32-bit design outperforms the state-of-the-art by 1.69x and 1.27x, respectively. These improvements become even larger when implementing higher data-path designs, such as 64-bit or 128-bit designs. Our non-DOM AES design is secure against Correlation Power Analysis (CPA) but vulnerable to Template Based Attack (TBA) when more than 1500 traces are considered. To enhance its resilience against side channel attacks (SCAs), we modified our design by adopting and further improving on the most recent countermeasure, i.e., Domain-Oriented Masking (DOM). The results demonstrate that incorporating DOM into our design enables it to withstand against both CPA and TBA. Besides, our simplified eight-stage and five-stage 1st-order DOM SBOX designs achieve a reduction in area of 9.9% and 6.9% compared to the original proposed designs, respectively.

Rowhammer is a security exploit used to cause bit errors DRAM chips. Newer DRAM technologies are becoming more vulnerable to rowhammer attacks, and existing protec- tion methods are starting to reach their limits. This thesis provides methods for DRAM characterization by means of reverse engineering, an in-depth analysis of vulnerable cells during rowhammer and a novel protection method. First the DRAM module is characterized by performing a retention test and a one- sided rowhammer attack throughout the memory. The resilience to rowhammer of vul- nerable victim cells has been analysed by using various data patterns in the victim cell itself in combination with its direct and diagonal neighbours. The impact of the pro- posed protection method is measured by flipping the data in the attacker row during a simulated rowhammer attack. Various rowhammer sequences are investigated. The results following the DRAM characterization show that only a one-sided rowham- mer attack is possible. Rows that impact one another during rowhammer come in pairs of two, one attacker row impacts only one neighbouring row. The results of the in-depth analysis of cells during rowhammer shows evidence of negative horizontal impact com- ing from uncharged neighbouring cells in the same row and negative diagonal impact coming from charged cells neighbouring the attacker cell in the attacker row. The hori- zontal impact is mirrored in symmetrical cells whilst the diagonal impact is not. Results following the proposed protection method experiments show that using the protection method improves the overall resilience to rowhammer ranging from 50%, 65% to 100% depending on the hammer sequence.

Over development of the past three decades, control systems in automobiles have undergone a significant transformation, shifting from mechanical devices to a multitude of interconnected computers that oversee sensors, drivers, and passengers. In today's modern vehicles, 50-80 independent computers, commonly referred to as Electronic Control Units (ECUs), form complex in-vehicle networks to facilitate communication among themselves. A widely adopted communication protocol in modern in-vehicle networks is the Controller Area Network (CAN). Security wasn't considered when the CAN protocol was designed in the mid-1980s, leaving it susceptible to cyber-attacks. In 2015, Charlie Miller and Chris Valasek successfully demonstrated a remote attack against a Jeep Cherokee, compromising critical components such as the steering wheel and braking system. This event prompted significant concern about the security of CAN networks in both academic and industrial circles.


In reaction to these challenges, researchers have formulated a variety of attacks targeting the CAN bus, encompassing Denial-of-Service (DoS) attacks, spoofing attacks, and more. Furthermore, significant efforts have been directed towards enhancing the security of CAN networks. These endeavors encompass the design of security architectures and intrusion detection systems. NXP developed the TJA115x secure CAN transceiver family, which offers protection against various types of attacks for Classical CAN and CAN FD communication without resorting to cryptography. Nonetheless, all existing researches are directed towards the Classical CAN and CAN FD protocols, leaving a notable gap in the exploration of security aspects concerning the latest CAN XL network.

This thesis focuses on enhancing the design of the TJA115x secure transceiver to support CAN XL protocol. The research comprises two main aspects: flooding detection and flooding prevention. To achieve flooding detection, a leaky buckets tree is introduced, enabling differentiation between normal frames and flooding frames, along with dynamic traffic control for each frame type. Additionally, the leaky bucket parameters are derived in formulaic form. For flooding prevention, two distinct strategies are devised to prevent flooding frames from dominating the bus. These strategies are compared in terms of throughput, latency, and availability. Finally, the proposed secure CAN XL transceiver is validated through software simulations and hardware experiments. The results demonstrate the exceptional performance of the CAN XL secure transceiver in blocking flooding attacks and safeguarding communications. These accomplishments are achieved with minimal memory overhead, and notably, without introducing any additional latency or bandwidth demands.

Forensics is the art of gathering evidence, which for electronics amounts to accurately recovering data. Often, this can only be archived with state-of-the-art hacking techniques.
However, replicating state-of-the-art research in hardware security can be difficult, due to the large number of components and connections. To counter this, a custom Printed Circuit Board (PCB) is presented, that aids with hardware attacks, and allows them to be executed in a reliable and reproducible way.
The PCB is targeted specifically towards hardware encrypted USB drives, and provides accessible ways to break out and interact with the target’s electrical components.

In the first part of this thesis, the design and fabrication of the platform, called LUPIn, short for Lawful Unlocking of PIN-protected USB drives, is established. The design integrates commonly-used components and functions, making it suitable for a wide range of different attacks and devices. It also incorporates robust and traceable connections to the target.
In the second part, LUPIn is verified by implementing it in a real attack. The target is a PIN-protected USB drive, which contains an IC performing key derivation. Since the debug port is not fully secured, a technique called Cold-Boot Stepping is used. This method is specifically designed to circumvent partially disabled debug ports.
To analyse the gathered data, it first must be filtered. This filtering is done using a graph-based algorithm.
In one crytographic function, an input parameter is used twice with different XOR masks. By analyzing all the filtered data, it is possible to find masked values, and use those to recover the original input value.

Concluding, a hardware tooling PCB (LUPIn) is successfully designed, assembled and tested. It proves to be a reliable platform for performing hardware attacks against encrypted USB drives. It makes development of hardware attacks simpler and less time-consuming.
In the validation of LUPIN, a real-life USB drive is successfully attacked. Thousands of RAM snapshots are collected and an algorithm is developed to filter this data. A single variable can be extracted, but it ultimately proved insufficient to fully crack the target.

This thesis focuses on identifying and classifying defects in STT-MRAM technology using novel and machine learning approaches. The thesis discusses the basic principles of STT-MRAM and the semiconductor chip manufacturing process and test stages. The research aims to develop novel methods and explore machine-learning approaches to diagnose defects in STT-MRAM devices. The current defect identification methodologies have shown certain cost, speed, and scalability limitations. The thesis presents DAT-based and ML-based Diagnosis methodologies to identify and classify STT-MRAM unique defects to address these challenges. The methods are evaluated and validated on experimental wafers performed at IMEC in Leuven, Belgium.

DAT-based Diagnosis involves automated defect identification in STT-MRAM based on identifying features automatically extracted from specialized measurements targeting the unique defects, Pinhole, Intermediate State, SAF Flip, and Back-Hopping. ML-based Diagnosis uses machine learning techniques to classify defects using MTJ features extracted from low-cost measurements. Data collected from electrical measurements on experimental STT-MRAM devices serve as the basis for evaluating the developed methodologies. The thesis also discusses data analysis, including data visualization, feature correlations, and outlier analysis for future research. Furthermore, a machine learning training process is performed, including hyperparameter optimization and evaluation using F-score and B-accuracy metrics to assess the model's performance and the ability to generalize on unseen data.

DAT-based Diagnosis aims to maximize the defect detection accuracy at the expense of measurement costs. In contrast, ML-based Diagnosis minimizes the measurement cost while maximizing the detection accuracy for robust and balanced classification. However, the DAT-based Diagnosis is not verified using PFA to validate the defect types identified by the developed methodology. Furthermore, the ML-based Diagnosis uses training data labeled by the unverified DAT-based Diagnosis approach to train machine learning models. Despite these limitations, the results have shown valuable insights into defect identification and classification, proving a robust framework for diagnosing STT-MRAM devices. Additionally, a scientific paper is submitted on march-based diagnosis, adapting the DAT-based Diagnosis method to industrial chips that are limited in extracting the identifying features.

Demand for smart, Internet-connected devices and other electronics has increased dramatically in recent years. This increase in demand for technological devices, driven by advancements in Artificial Intelligence (AI), the Internet of Things (IoT), and autonomous systems, has exposed the digital system to potential security threats. As more devices access personal data, data protection and security have become increasingly challenging. The rise in security incidents, such as the MOVEit attack and the NeBu data breach, highlights the urgency for better security systems. Malicious attacks can manifest at different levels, ranging from the network and system to the circuit level. Power side-channel attacks, which exploit variations in power consumption to obtain sensitive information, have proven effective against modern cryptographic implementations. In response to the threats posed by such attacks, researchers have diligently focused on devising countermeasures. Current research efforts focus on developing these countermeasures, yet evaluation only happens in pre-silicon scenarios in simulation or on an FPGA. Evaluating the effectiveness of those countermeasures on real Systems on Chips (SoCs) is challenging.

The thesis introduces a novel framework to bridge the gap between pre and post-silicon power side channel assessment, allowing accurate characterization and comparison of cryptographic designs before and after manufacturing. This approach aims to provide comprehensive profiling and ensure the security of future cryptographic designs. The suggested platform was verified by employing a series of different versions of the Advanced Encryption Standard (AES) algorithm that were integrated into a full System on Chip (SoC). As a metric for determining whether or not the proposed platform is suitable, attacability is being measured via correlation power analysis (CPA). Pre-silicon enables the evaluation of each AES core in isolation from the other components of the system, hence having noise-free power traces. However, in post-silicon, in order to provide a correct analysis, the platform incorporates a wide variety of features, such as automation execution, trace alignment, and noise reduction of power traces. In order to improve the automated execution process, a Left Feedback Shift Register (LFSR) has been devised to introduce a level of randomness in the encrypted messages and keys used by the cryptographic engine. In the context of trace alignment, the platform has been specifically built to include a trigger signal that serves the purpose of identifying the start/stop of the execution. Clock-gating is used as a means of mitigating noise by freezing the operation of additional cores, hence preventing the generation of extraneous auditory disturbances. In addition, the suggested approach is specifically tailored for the manufacturing process using the 40nm TSMC technology, including a simulation evaluation. Finally, to facilitate power measurements on the platform, custom printed circuit boards(PCB's) and a software backend were designed to support real life measurements and the final correlation of the pre and post-silicon power side channel behaviour. The results of our study suggest that both Pre-silicon (i.e., standalone evaluation) and Post-silicon (i.e., system evaluation) provide similar levels of accuracy in assessing attackability.

The increasing advancements in quantum computing have led to an increasing danger for the cyberspace. The current cryptographic algorithms that are used to enable secure communication across insecure channels have the potential to be brute-forced by sufficiently powerful quantum computers, endangering the security of many electronic devices and protocols that use popular algorithms such as RSA. Although it is not feasible currently, these advancements in quantum computing are accelerating rapidly and the impact this could have on the security of the cyberspace is too great, therefore countermeasures must be considered. To protect against this threat, the National Institute of Standards and Technology (NIST) has started an initiative to work towards standardizing quantum-resistant cryptoschemes before the advancements in quantum computing reach such a level. This has led to a great amount of collaboration by researchers to develop and analyze the security of these quantum-proof schemes over the past six years.

This thesis explores the various post-quantum cryptoschemes that are currently being considered, outlining their differences and the potential advantage of using each scheme. While all of the current submissions are required to have a software implementation to be part of the submission, this is not the case for a hardware implementation. Hardware implementations can have different vulnerabilities than software implementations and, due to this, having one or preferably multiple hardware implementations available for these schemes would greatly advance the security analysis that can be performed for these candidates. Therefore, this thesis describes the hardware implementation process of one such scheme, NTRU, one of the longest standing lattice-based schemes, since this danger of quantum computing is equally dangerous for the many hardware devices and chips that are used worldwide. It discusses the various design decisions that have been made during the implementation and presents all functions that have been implemented to perform the encryption and decryption step of the deterministic public key encryption (DPKE) algorithm of NTRU. This implementation combines work that has been done for the previous NTRU submissions and adds additional logic to support the new and adjusted parts of the current NTRU algorithm. The results show a fully functional encryption and decryption functionality of the NTRU cryptoscheme where the full encryption function can be performed in 3038 clock cycles while still maintaining a considerably low area usage, showing a speedup of 16 when compared to an optimized software implementation. Aside from this result, this thesis also provides several potential adjustments to the hardware implementation that can be made to reduce the decryption time at the cost of additional area so that the hardware can be tuned depending on the desired specifications.

Resistive Random-Access Memory (RRAM) is an emerging memory technology that has the possibility to compete with mainstream memory technologies such as Dynamic Random-Access Memory (DRAM) and flash memory. The reason why RRAM has not seen mass adoption yet is due to its defect-prone nature. The resistance of RRAM can assume any value within its operating range and its resistance can be divided into five states instead of the regular two logic states. Conventional test techniques are incapable of detecting unique faults due to their inability to distinguish between all five cell states, resulting in a large number of test escapes. Therefore, new test methods, such as Design-For-Testability (DFT), need to be developed to reduce the number of test escapes and ensure customer satisfaction. This work proposes two new DFTs: Parallel-Reference Read (PRR) and Closed-Loop Write (CLW). The PRR DFT is a replacement for the regular read circuit, which enables the detection of all five cell states, while the CLW DFT is an addition to the regular write circuit, which introduces feedback during the write operation. From these two DFTs, the PRR DFT is selected for further development and its design is validated. From the validation, it is concluded that the PRR DFT can detect all five cell states. Moreover, under process variations, the PRR DFT will provide the correct output in 95.90% of the cases. Furthermore, the PRR DFT improves the overall resistive-defect detection capability by 14.79% when compared to a regular read circuit. Finally, the PRR DFT offers 100% identified fault coverage while only requiring 4N write operations, 5N read operations and an area overhead of 14N_c transistors, where N and N_c are the total number of cells and the total number of columns in the RRAM array, respectively.

As the new generation of neural networks, Spiking Neural Network architectures
executes on specialized Neuromorphic devices. The mapping of Spiking Neural Network architectures affects the power consumption and performance of the system. The target platform of the thesis is a hardware platform with Neuromorphic Arrays with columns for neural signal processing.
The explorations for the mapping methods are based on VPR, an open-source academic CAD tool for FPGA architecture exploration. The packing of VPR is used for mapping neurons to Neuromorphic Arrays. VPR includes two levels of mapping: pins and neurons.
An evaluation of the mapping methods is established. Based on the evaluation, the optimized mapping solution is generated. Modifications are made in VPR to adapt to SNN architectures. An Activity-Criticality input file is added to the VPR flow for the optimized mapping solution.

Spin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as one of the most promising non-volatile memory (NVM) technologies, which has the potential to replace the traditional memories in the modern memory hierarchy. Due to some advantages such as non-volatility, fast access speed, low leakage power and high density, more and more research attention is being paid to STT-MRAM. To enable the mass production of STT-MRAM, high-quality and cost-efficient test solutions are the prerequisites. In this thesis, the comprehensive investigation for testing interconnect and contact defects in STT-MRAMs will be presented. The complete defect space for interconnect and contact defects in STT-MRAMs is systematically defined, which are modelled as linear resistors. All theoretically possible faults are defined in a fault space, followed by a methodology to validate these faults under inter-cell magnetic coupling in the presence of defined defects. In this way, accurate fault modelling is performed to guarantee the occurrence of realistic faults in STT-MRAMs. We observed the specific STT-MRAM fault model—passive neighborhood pattern sensitive fault (PNPSF). Based on the fault validation results, an effective march test algorithm(7N) is proposed for interconnect and contact defects in STT-MRAMs.

Some server hosters facilitate cyber crime either intentionally (so called “bulletproof hosters”) or unintentionally (“bad hosters”). When dealing with uncooperative hosters during forensic investigations, it may sometimes be necessary to collect data or information on the servers without help from the owner of the server. Data within the RAM might prove insightful in, for example, determining active processes or reveal crypto graphically interesting information like encryption keys. The thesis explains key concepts within memory organization and the PCIe standard.Afterwards, it discusses several techniques for RAM acquisition and categorizes and evaluates them using a model-based approach. The thesis then dives deeper into DMA-based memory acquisition using PCIe and proposes several improvements to current DMA attacks in order to create a better memory acquisition technique. A novel memory acquisition technique is created by hot-plugging aPCIe device and skipping over the regular enumeration procedure. This techniqueal lows the memory acquisition to be executed without a reboot and provides a stealth approach to accessing the memory.  

As of 2021, the world economic forum deems cyber-security failures as one of the most potent threats to the world. According to a McAfee report, the cost of cybercrimes in 2020 reached nearly 1 trillion US dollars, which was around 50 percent more than what it was in 2018. Exacerbating the already mammoth financial implication of such a failure is the ever-growing diversity in cyber attacks. Side-channel analysis is one such attack type wherein the information leaked via the implementation of a cryptographic algorithm is leveraged to obtain secret data, rather than any weaknesses in the cryptographic algorithm itself. This leaked information, amongst others, can be in terms of power, EM radiation, or the time taken to perform a cryptographic operation. Countermeasures against such side-channel attacks aim at reducing the amount of information leaked via the side channels or reducing the correlation between the secret operations and the information leaked. Manufacturing the chip is often a prerequisite for evaluating the efficacy of such countermeasures, which is a costly and time-consuming process. Thus, the security evaluation of a design has a substantial impact on the design cost and the time to market. In case the design does not meet minimum security requirements, it has to be redesigned and manufactured, increasing not only costs but also the design time considerably. Hence, there is a need for pre-silicon leakage assessment tools that can provide designers a sense of certainty about the security aspects of their design. However, the existing pre-silicon leakage assessment tools are either deemed unreliable or too slow to be used to perform power leakage assessment, which is the problem this thesis aims to ameliorate. This thesis explores the use of generative adversarial networks (GANs) for generating synthetic power traces. Generative deep learning has been used in various domains like computer vision, audio, and even for medical data like ECG. GANs have been introduced in the context of side-channel attacks to enlarge the size of the profiling dataset for carrying out profiled side-channel attacks. In this work, we propose a robust methodology to condition and train GANs to generate power traces that can be used to carry out leakage assessment. This methodology can even be extended to support the design space exploration of countermeasures by providing reliable leakage assessment at design time. The generated power traces are not only indistinguishable but also as attackable as the real traces. The conditioning technique helps the GAN to generalize to various scenarios and the proposed framework provides a speed-up of around 140 times over traditional CAD methods to simulate power traces while maintaining their structure and accuracy.

The issue of securing microchip designs against hardware attacks has grown in magnitude as more and more embedded systems are deployed in hostile environments, where security measures have to be taken to prevent attackers from accessing unwanted information.
The first step in solving this problem is gaining awareness of the security vulnerabilities in a design, which can be done through a fault injection campaign. Current solutions tackle the issue by either requiring silicon manufacturing for every prototype, which is expensive, or simulating faults using a model of the device under test and of the possible faults being injected, which takes a considerable amount of time. Some hybrid solutions have been developed to improve this aspect (namely, by using FPGAs to implement the device and injecting faults on it instead), but they still require some form of specialized hardware to operate.
Moreover, a gap still remains between the results from these tools and the work necessary to update the design and mitigate the vulnerabiliies found. Results usually reference cells in the netlist, while the development is mostly done in a high-level hardware descriptive language.
This thesis proposes two improvements to the currently existing workflow: first, it explores the effectiveness of equivalence checking in tracing individual gates in the netlist representation back to the RTL lines that generated them, and second, it builds on the simulation-based fault injection approach by introducing a formal framework to prove the presence or absence of successful faults.
The results show that equivalence checking can significantly increase the number of cells recognized as results of individual RTL lines of code, enabling a designer to better pinpoint which components should be hardened against fault injection attacks. In terms of fault identification, the framework described can reduce the number of faults to be simulated down to 2% of the number necessary to exhaustively check a design for possible vulnerabilities, greatly speeding up existing simulation-based approaches.

The adoption of Microprocessors is increasingly diversifying to several embedded and mo- bile devices. Growingly they can also be found in Smart Cards, RFID tags, SIM cards, Pay TVs, identity cards and passports. These devices store, processes and transact sensitive information like social security numbers and credit card numbers. Ensuring security of such systems is of paramount importance. Attackers use Fault injection as one of the tech- niques to induce faults into the processor in order to gain access to the sensitive information to abuse it. Vulnerability Analysis of the processors can help chip designers to counteract some of these risks. This analysis can be achieved by investigating the resulting fault space upon exhaustive simulation of fault injection attacks. Therefore, efficient tools and frame- works are needed to provide such security verification, where critical vulnerabilities can be discover and mitigated at design-time. Multiple tools and frameworks for simulation based fault injection of hardware designs are available in literature, each with their own shortcomings. Two main strategies have been proposed in literature, one based on tool manipulation while other based on code modifica- tion. Applying tool manipulation, a designer can automate the process to inject faults in the system and obtain simulation results in a fast manner. However, this approach is limited by the features provided by the tool, which makes difficult to explore many different fault models. Additionally, in most cases, results require manual inspection to be interpreted. The latter approach, which is code modification, can inserts agents to cause the faults (i.e., saboteurs) or vary the existing design (i.e., mutants). It allows designers to achieve a high degree of control in terms of the type of fault and the injection method. However, current so- lutions are limited to a specific language, design or scenario. Hence, the literature presents many different strategies and tools to apply faults to investigate hardware behavior, but still the interpretation of vulnerabilities related to processors are not considered in such tools. Moreover, a complete automated framework capable to get a design and process it to report vulnerabilities and behavior issues related to security is still needed. This thesis proposes a framework that provides a complete toolset able to evaluate vulner- abilities of processors in hardware description language. Its main steps comprises design instrumentation, simulation based fault injection and automatic fault classification. RISC-V is chosen as the target architecture due to its open source nature and its increasing adoption by academia and industry. Code profiling was carried out on the frameworks to identify bot- tlenecks to performance. The results were used to optimise execution time of simulations using the framework. Performing Fault injection campaigns requires running simulations in the order of 100k, which requires systems with high computing power to complete them in reasonable time. Therefore, multiprocessor support was implemented in simulation frame- work, which could be enabled or disabled during the injection campaign. The framework was used to perform fault injection campaigns on PicoRV32 and DarkRISCV processors. A comparison between the processors is made based on their major failure signatures. Anal- ysis of finding design constructs in the processors which cause the major failure signatures was carried out. The results from this vulnerability analysis are used to propose software and hardware countermeasures to make the design more robust against fault injection.