Faster Test Development through Accurate Digital Twinning of Loadboards

Abstract

The increasing complexity of Integrated Circuits (ICs) and stringent quality requirements in industries like automotive have contributed to increasing test development time. Virtual testing methodologies, such as AMS-VT, can be used for pre-silicon debugging of test programs, optimizing the test development process. However, AMS-VT has shown limitations in their usage due to the absence of accurate loadboard models, especially in capturing site-to-site variations. To address the lack of an accurate loadboard model for pre-silicon debugging, this research proposes a framework for generating an accurate loadboard model by integrating parasitic effects and possible reflections under real-world conditions.

The proposed framework consists of three main stages. The first stage is an automated netlist generation phase, during which an ideal single-site netlist is created from a multisite loadboard schematic. The ideal netlist is generated considering the AMS-VT environment so that it can be seamlessly integrated into the current virtual testing environment. In the next stage, Cadence PowerSI, which is an Electronic design automation (EDA) tool for parasitic extraction, is automated to extract the parasitics (R, L, G, and C) for all the channels included in the ideal netlist. Finally, in the last stage, a methodology is developed to integrate the parasitics and reflection due to impedance mismatch in the ideal netlist. To improve the accuracy, a static model of the relay was developed that considers its characteristics, such as on-state resistance and off-state current leakage. All these stages are then automated and combined to create a framework that can effectively generate an accurate loadboard netlist that predicts site-to-site variations.

The framework is then validated, with each stage verified independently. The generated ideal single-site netlist was verified against a golden simulation. This verification displayed that the functionality of the generated netlist was accurate and could integrate with AMS-VT seamlessly. The parasitics extracted from PowerSI were validated using a test Printed Circuit Board (PCB) with multiple configurations. This showed that the simulation results using extracted parasitics were within 1% error compared to the IR drop analysis. The relay model was also validated by comparing it with its datasheet, proving that the model accurately considered the physical characteristics. The third stage was then validated by comparing it with PSpice simulations, demonstrating that the model's results were accurate, with the maximum error being below 1.6% for multiple voltages and frequencies. The complete framework was then validated against a physical loadboard, showing maximum errors of less than 2% across all sites and improved timing accuracy for pulse width, reducing it to 0.41% for the proposed framework from 1.6% for the previous methodology. This validation proved that the loadboard generated by the framework accurately modelled parasitics and reflections. The model also accurately accounted for temperature variations, demonstrating its effectiveness in changing operating conditions. By introducing this framework to generate an accurate loadboard model, this research enables a virtual testing environment for faster and more reliable test development, reducing the time-to-market for semiconductor products.