The demand for embedded devices, such as intelligent sensors, smartwatches, medical implants, and computing chips in cars, has been rising steadily in the past and is expected to continue for the coming decade. Their high and increasing degree of connectivity expands the attack surface for attackers, which is exaggerated by their physical accessibility. This makes them particularly vulnerable to invasive attacks. Compounding these risks is the growing reliance on third-party software. An example of such risks can be seen in the recent incident where a software solution from the company CrowdStrike, integrated into the Windows Operating System (OS), caused a major global outage that left many airports, hospitals, banks, and government departments worldwide unable to operate. The Guardian reports that this incident affected 8.5 million Windows machines and resulted in an estimated financial loss of 5.4 billion USD for companies in the US alone. Similar risks exist for OSs for embedded devices. These devices do not run general-purpose OSs like Windows, however, in their very nature they are similar. They provide a runtime abstraction for user processes and manage resources for which the OS requires higher privileges. FreeRTOS is a popular embedded OS for resource-constrained devices, also offering real-time capabilities, making it a Real-Time Operating System (RTOS). Meanwhile, RISC-V, a relatively new Instruction Set Architecture (ISA), is gaining popularity due to its open-source philosophy. However, despite the increasing popularity of RISC-V and the widespread use of FreeRTOS, there is a lack of comprehensive security support for FreeRTOS on RISC-V platforms.

This thesis addresses the lack of security for malicious third-party applications and presents a novel FreeRTOS implementation method on a RISC-V embedded system platform. The security of FreeRTOS is enhanced by leveraging the Physical Memory Protection (PMP) feature of RISC-V. The primary contribution involves the FreeRTOS kernel dynamically manage the access rights using PMP, preventing malicious tasks from causing harm. This dramatically improves the security, because the flat memory structure inherent to FreeRTOS is prone to being readily exploited and compromised by attackers. Further, an overview of known attacks on embedded systems and countermeasures is presented, a subset of which are explored in more detail. A secure platform is proposed that aims to demonstrate a holistic approach to integrate the FreeRTOS with PMP support into a System-on-Chip (SoC). Then, the FreeRTOS platform is augmented by a secure boot procedure and a memory encryption unit that ensures the integrity and confidentiality of the external memory. This encryption unit uses the Prince encryption scheme and is elegantly combined with RISC-V’s PMP functionality. Unused bits in the PMP configuration registers are used to control the encryption selectively for single PMP memory regions. Moreover, an address-based encryption mode for this unit is proposed that addresses the weakness that plaintext data is always encrypted to the same ciphertext. This is problematic because an attacker could analyze the structure of the ciphertext and copy the ciphertext of memory cells with known plaintext. The effectiveness of the PMP task isolation is demonstrated by simulating malicious tasks that try to access specific data addresses in the memory of other tasks and the kernel. This setup imitates real-life attack scenarios, assuming the addresses have been exposed to the malicious task through reverse-engineering of the application code. The secure boot is validated by implementing the design on an FPGA and manually tampering the memory, resulting in a failed boot-up. Additionally, the impact of the PMP integration on the real-time capabilities of FreeRTOS is investigated more thoroughly by evaluating real-time metrics: task switch time, access time for shared resources using a mutex (a software construct to avoid access collisions), and dynamic memory allocation. The system design incorporates a RISC-V core named CV32E40S, an open-source core from OpenHW Group. All the security enhancements were run on hardware with a varying number of active PMP regions. In the worst-case scenario, using 64 PMP regions results in a 2.1x increase in task switch time, a 2.4x increase in the time to access shared resources using a mutex, and a 1.7x increase in memory allocation time. The area of the CV32E40S, measured in Look-Up-Tables (LUTs), increases with the number of regions: a 2.2x increase for 16 regions, 3.4x for 32 regions, and 5.4x for 64 regions, compared to the core configuration without PMP. Despite these increases, it remains within an acceptable range relative to the total area of the SoC including cache memory and peripherals.

Chip forensics has become an important aspect of law enforcement for retrieving data from data carriers. Improving data encryption techniques, smaller technology nodes and increasing chip design complexity instigate the constant need for new software and hardware hacking methods. The work presented in this thesis investigates the potential of a new hardware hacking method named backside contacting. This method aims to connect a probe to one of the bottom interconnects through the backside to listen to the signals sent over that interconnect.
For this purpose, a recipe has been developed. This recipe is a workflow of numerous processes and steps. Several methods like delayering, cross-sectioning and infra-red (IR) imaging were developed to obtain information about the layout and technology of the chip. Atomic layer deposition (ALD), induction coupled plasma enhanced chemical vapour deposition (ICPECVD) and a focussed ion beam (FIB) were used to create structures on the die, in order to realize a backside interconnect. Finally, various setups were built to test the chip throughout the recipe.
The study shows that each step is possible without losing the data on the chip. The yield of surviving chips after each step, however, should be increased to establish a full backside contact while keeping the chip alive. The study also indicates that there remains considerable potential for improvement within each step. The results are promising and justify further research into the method of backside contacting.

This thesis presents the process of design and implementation of a power grid simulator, with focus on the power grid configuration and load forecasting as part of a larger project. The overarching project aims to address the increasing complexity of power grids and the occurence of grid congestion. Its primary objective is to visualize these issues for educational purposes. For this subsystem, the specific goal is to provide a grid configuration, all necessary data to simulate it, and load predictions for the grid.

The n-body problem is the simulation of pair-wise interactions between n objects. This problem appears in many forms, with the classic example being the modeling of gravitational forces between point masses, necessary for cosmological simulations. Many approximation approaches have been devised to reduce the complexity of this problem.

t-SNE is a data visualization method that requires repeatedly solving a variant of the n-body problem. A recent paper (An Efficient Dual-Hierarchy t-SNE Minimization, van de Ruit et. al.) proposes a novel algorithm that outperforms other t-SNE minimization methods on medium-scale datasets. The report proves the viability of a dual-traversal method that uses an embedding tree to emit forces and an independent field tree to collect forces. Because the embedding tree is a Linear-BVH and the field tree is an orthtree built to a fixed depth, the overall algorithm has linear complexity.

This thesis demonstrates how the dual-tree approach can be adapted for gravitational n-body simulations. Following this, it measures the performance against similar implementations of other algorithms and shows that while the adapted Dual Hierarchy approach is faster than Barnes-Hut, it is outperformed by the Fast Multipole Method on realistic large-scale cosmological datasets.

Resistive random access memory (RRAM) is an emerging memory technology that has the potential to replace dynamic random access memory (DRAM) or FLASH. The current memory technology suffer from scalability issues. RRAM can be used as potential replacement for Flash and DRAM. RRAM stores information using resistance states instead of charge. RRAM is non-volatile memory, power efficient, scalable and compatible with the current CMOS process.
Before RRAM can be commercialized the quality of RRAM devices needs to be guaranteed. For this we need to diagnose RRAM devices. The diagnosis allows us to improve the manufacturing process as well as built defect models for memory testing. The traditional fault models do not incorporate the non-linear behaviour of the RRAM device. As a result, tests are created for the wrong test space resulting in a lower yield and more test escapes. To increase the yield and create more reliable fault models, defect models that incorporate the physical defect of the RRAM device are required. To ensure the manufacturing quality of the RRAM devices and for memory testing of RRAM the characterization and diagnosis of RRAM is required. The electrical characterization of RRAM is cheap, fast and is used to evaluate the performance of RRAM. For diagnosis electrical characterization has not been used before.
This work uses the electrical characterization of RRAM to automatically identify defective RRAM devices which can be used for diagnosis. For the defect identification, the key parameters are determined. To assess the performance of the defect identification algorithms the RRAM devices are labelled manually. In total five methods have been implemented to automatically label defective RRAM devices. A statistical analysis is performed on the RRAM devices. Using the labelled data the devices are compared to a nominal device to identify defects in RRAM. Furthermore, K-means, KNN and a CNN algorithm is applied to RRAM. The classification algorithms allow the automatic identification of defective RRAM devices which can be used for diagnosis.
The metrics used for the statistical analysis are insufficient to accurately identify defective RRAM devices. The nominal device method classifies 81% of the device correctly using the euclidean algorithm. The best performance is obtained for the supervised learning algorithm. K-NN classifies 94% of the cycles correct and 84% of the devices. If the data is not labelled the unsupervised learning algorithm can be used. Kmeans classifies 79.6% of the devices correctly which is slightly worse than K-NN. The CNN classifies 67% of the devices correctly using 20 epochs. However, the CNN has not yet been optimized and needs to be improved. For unlabelled data, the unsupervised learning algorithm should be used and for labelled data the K-NN. The electrical characterization of RRAM devices using machine learning looks promising and is much cheaper compared to optical characterization and memory tests. If in the future the defective devices can be linked to the underlying defect, this will lead to cheaper diagnosis of RRAM devices and allow the creation of accurate fault models.

Manufacturers of CubeSats prefer the use of COTS electronic components such as microcontrollers (MCU) and SDRAM but these components are vulnerable to errors caused by radiation. A specific type of error caused by radiation are soft errors which can be corrected by Error Detection and Correction (EDAC) methods. Unfortunately, it is uncommon for MCUs to have an (optimal) EDAC solution integrated in their memory controller. In these cases an external solution is required.
This work proposes a generic methodology towards transparent FPGA-based correction of soft errors that can be applied given a specific microcontroller and its off-chip main memory. To determine how powerful the EDAC solution must be the methodology uses reliability models to evaluate the MTTF of the memory system. Then, the methodology describes how the EDAC logic must be designed in the FPGA fabric such that the FPGA and its EDAC logic are transparent to the MCU. A method to periodically scrub the memory transparently to the processor is also included.
A major trade-off of the FPGA based design is that it requires the clock of the MCU memory controller to be lowered to meet the timing requirements of the SDRAM interface. For some designs it is also necessary to lower the memory capacity or to use more SDRAM devices to store the ECC parity bits.
Lastly, a hardware demonstrator was built to provide EDAC capabilities to the onboard computer developed by ISISPACE. The design consisting of an ARM9 microcontroller, an FPGA and two SDRAM devices is capable of correcting a single error in each byte of the 32- bit SDRAM interface of the MCU and can scrub the entire memory in 33 seconds. Software benchmarks showed that computing performance is about half of the original board as a result of halving the memory controller clock.

In recent years, computers have found their way into nearly every part of life. This led to the creation of many embedded devices, which are usually quite different from the more commonly known computers and each other. The cause of this is the diversity in constraints that are placed on these devices, in terms of size, weight, energy consumption and more. It is important to test and analyse these embedded systems, to avoid malicious actors to gain control of these systems, or for bugs in the code running on these systems to cause problems. In contrast to other computers, embedded systems are often tightly integrated with their environment and are designed to control it. However, there still are major challenges when analysing these systems, just because of their tight integration with the environment. When executing the code out of the environment it was intended for, it often functions differently, if at all. Current solutions attempt to solve this problem in various ways, but they all fail to create a system that is general and flexible. As such, this project set out to find a methodology that solves this problem in an automated way, while ensuring the device's code executes accurately. This thesis presents a methodology to solve this problem in a general and flexible way, using symbolic execution. By using symbolic execution to handle interaction with the environment, the system can realistically and generally emulate embedded devices. Additionally, symbolic states are made concrete after a while, to continue executing concretely. When the system is executing concretely, user-defined hooks can be executed, which can be used to further instrument the process, allowing for great flexibility. Such extensions could be used to attach a debugger to the system, or by redirection output from a serial connection to a file. We conduct an empirical study to find that the system emulates accurately, reaching a nearly identical result to the same code running on real hardware, using four diverse samples. Additionally, we compare the system against Jetset, a system that attempts to solve a similar problem using just symbolic execution, and find that, although our system is considerably slower, it remains accurate. The difference in performance is primarily due to their system being more tightly integrated. Still, the added flexibility our system provides makes it more suitable to extend with further analyses, and thus might make it preferable in some situations. Finally, we provide the source code of an implementation of the system to allow researchers to continue developing and improving this system.

We propose a novel, dynamic analysis-based detection solution for formjackers. The operating principle of these formjackers, or card skimmers on the web, is typically simple, yet effective: when making a payment on webshop that has been infected with a formjacker, the submitted payment information is not just transmitted to the webshop, but also silently to the involved malicious actor. Incidents in the past few years with large numbers of potentially affected customers, in the order of hundreds of thousands to millions, and high fines, in the order of tens of millions, have shown the urgency of addressing the issue of card skimming on the web. Currently, the state of the art in detecting formjackers is that of the cybersecurity industry, whose proprietary detection strategies appear to heavily rely on classical, static-analysis techniques. A drawback of these techniques is that they are less suited to detect new or unknown strands of formjackers. To advance the state of the art and enable a comprehensive, large-scale study of formjackers on the web, we wish to go beyond the traditional `Indicators of Compromise' approach. Instead of building on relatively shallow indicators, such as what formjacker typically look like, or which domains are commonly associated with formjacking campaigns, we propose to look at the underlying, more rudimentary behavior of formjackers, such as accessing data entered into the page. To this end, we introduce and study a detection strategy that ties into these more fundamental behavioral patterns of formjackers by applying dynamic analysis of client-side JavaScript. As an important prerequisite in dynamic analysis, we identify which conditions must be satisfied to elicit malicious behavior in formjackers. We implement two types of dynamic analysis, showing how these conditions can be met in practice. Finally, by crawling various collections of URLs we study the extent to which the proposed detection solution is suited to detect formjackers.

Side-channel Attacks can be performed in various ways by measuring the power consumption, the electromagnetic emission, or even by measuring an algorithm's execution time on the targeted device. More or less sophisticated methods can be used to utilize this information in order to perform a Side-channel attack, more specifically by training Machine Learning models with traces acquired from a profiling target or by directly performing statistical analysis to a black box target. Of course, performing a successful attack in a black box scenario requires large amounts of traces, even for unprotected implementations. On the other hand, with the state of the art Machine Learning methods, a successful Side-channel attack can be performed by acquiring a smaller number of traces. Nevertheless, for every case, in order to perform a Side-channel Attack, first traces have to be acquired from the target. This acquisition phase is a time-consuming and computationally expensive procedure that requires hardware tools and human supervision. For this reason, in this thesis, we investigate if synthetic Side-channel traces can be generated when the Hamming Weight (HW) model is used as a power model. To generate synthetic traces, we use Generative Adversarial Neural Networks (GANs), a Deep Learning approach that is the state-of-the-art augmentation method in many other fields, especially in Computer Vision. Therefore, we introduce a pipeline to define the architecture of the GANs but also to improve and evaluate it. In other words, we investigate novel ways to introduce new software tools to minimize the time and processing power needed to perform a successful Side-channel attack. Since the HW model is used, the Side-channel datasets follow a specific binomial class distribution, and by using GANs, we can augment the dataset by altering this distribution according to our will. For this reason, before performing data augmentation, we investigate how the profiling models' performance is affected by the trace's class distribution. Next, we use our pipeline to define two GAN architectures: a shallow one able to generate high-quality synthetic traces for unprotected implementations and an enhanced second architecture that can generate synthetic traces even when mild countermeasures such as jittering are in place, by being more stable but also more computationally expensive. We apply the pipeline's methodology on unprotected datasets and on datasets with mild countermeasures such as jittering and we made some steps leveraging GANs to solve the task of augmenting dataset that consist of Side-channel traces. In this way, we managed to compare the GANs with the well established Synthetic Minority Oversampling Technique (SMOTE), and we observed that GANs achieved similar performance with SMOTE and, in some cases, better. We apply the pipeline's methodology on unprotected datasets and on datasets with mild countermeasures such as jittering and we made some steps leveraging GANs to solve the task of augmenting dataset that consist of Side-channel traces. In this way, we managed to compare the GANs with the well established Synthetic Minority Oversampling Technique (SMOTE), and we observed that GANs achieved similar performance with SMOTE and, in some cases, better. This thesis showed that GANs can generate high-quality synthetic traces for unprotected implementations and implementations with mild countermeasures, which means that there is space for future investigation in this direction that might lead to more sophisticated architectures able to perform data augmentation in the Side-channel Analysis field.

Modern implementations of encryption algorithms on CPU’s that use frequent memory lookups of precomputed functions, are vulnerable to Cache based Side­Channel Attacks. The ρ­-VEX processor, a runtime reconfigurable VLIW processor developed at the Computer and Quantum Engineering department at the TU Delft was identified to possibly allow for special countermeasure implementations against Cache Attacks, because of its unique Cache architecture, hardware context switching and timing behaviour. In this thesis, the possibility to use the runtime reconfigurability against Cache based Side­Channel Attacks of the ρ-­VEX processor is investigated. The ability for the ρ­-VEX to alter its execution time based on configuration size, interfere with its own Cache state based on configuration and dynamically switch contexts between Caches are explored. Simple variants of the attacks Prime+Probe, Evict+Time and Final Round Collision Attack are implemented and ran on two setups that simulate practical scenarios of the ρ­-VEX. These are a standalone setup and a setup with a second context sharing the processor with an arbitrary workload based on the PowerStone benchmarks, which causes noise by itself and can amplify countermeasures. The ρ-­VEX was instanced on the Genesys2 FPGA development board. We have shown an implementation of timing noise through configuration size variations called nLane increased the amount of samples required for the timing Attacks Evict+Time and Final Round Collision to around 800x more traces. An implementation of access noise through swapping contexts called CacheSwap achieved 800x more traces for Evict+Time and 225x more traces for Final Round Collision when executed in a shared processor. The effect on Prime+Probe was only strong for higher chances to swap, but the overhead for these percentages was considered too high. An implementation of isolating lookups over private Caches, called ScatterRound, had additional benefits aside from preventing collisions. It made our Evict+Time Attack take 160x, Prime+Probe Attack 175x and Final Round Collision Attack 225x as many samples to be successful. We have shown that the overhead associated with 10% n­Lane and 10% CacheSwap was reasonable, but ScatterRound was concluded to require a specific execution setup to achieve performance costs that are acceptable.

Resistive RAM, or RRAM, is one of the emerging non-volatile memory (NVM) technologies, which could be used in the near future to fill the gap in the memory hierarchy between dynamic RAM (DRAM) and Flash, or even completely replace Flash. RRAM operates faster than Flash, but is still non-volatile, which enables it to be used in a dense 3D NVM array. It is also a suitable candidate for computation-in-memory, neuromorphic computing and reconfigurable computing. However, the show stopping problem of RRAM is that it suffers from unique defects, which is the reason why RRAM is still not widely commercially adopted. These defects differ from those that appear in CMOS technology, due to the arbitrary nature of the forming process. They can not be detected by conventional tests and cause defective devices to go unnoticed. Therefore, new tests need to be developed that properly include the physics of a defective device in a RRAM model. Device-aware testing (DAT) is the state-of-the-art solution to this problem. By accounting for the unique physics of an RRAM device, DAT is able to detect unique RRAM defects. However, DAT bases its results on relatively compact electrical models, which do not account for randomness present in e.g. the forming of the filament and local temperature fluctuations. Meanwhile, many low-level physical models exist already that can model this randomness and provide accurate insights into the physical specifics of RRAM. These models do, however, hardly ever analyze the effects of defects. The contribution of this work is to expand and improve one of the state-of-the-art physical models to analyse manufacturing defects on a low, near atomic-level scale. For the first time, the characteristics of a defect can be described in the physical shape of the defect, rather than only the electrical consequences of a black box device. This enables deep level analysis and characterization of defects, the results of which improves DAT to detect even more unique defects. The model is applied to four types of RRAM-related defects: oxygen vacancy density fluctuation, oxide thickness variation, electrode roughness, and contamination by impurities. The effect of the defects on the conductivity of the device are observed and explained, and their unique non-linear behavior is confirmed by simulation. Dynamic defects are not yet included, but the model does provide an extensive static characterization of unique RRAM defects, providing insights into their behavior and improving the quality of DAT. Finally, a discussion is presented which criticizes the reproducability of the referenced defect-free model, but also shows the potential of this work's model to be improved.

Pavement undergoes a fast deterioration process either due to the damages induced by weather conditions, an increase in traffic flow and load, or passive factors like aging of infrastructure. Thus requiring periodic rehabilitation measures to maintain the condition of the underlying asset. Since damages on the asphalt road, impose economic setbacks and concern for the users, governmental authorities are looking for a proactive approach to detect and classify distresses in their "early" stages. As a reason, governmental authorities like the Province of Zuid-Holland (PZH) yearly inspect the road network, which was optimal until now, but as the traffic flows are increasing and weather conditions are worsening, a new approach is required to mitigate the need for a frequent, cost-effective and reliable inspection method. Modern data sources such as smartphones are the biggest data generators. Having an intriguing number of sensors and in-built features, governmental and private authorities are just starting to acknowledge the potential of such crowd-sourced data generators. In this research data-types like vibration and imagery were gathered and synthesized to assess the efficiency and accuracy of the 3 data-driven models. A 7-step methodology was implemented to build all the machine learning models. At first, vibration data was gathered to detect road anomalies and predict the International Roughness Index (IRI), by building a Random Forest decision tree. Secondly, a Convolution Neural Network (CNN) was constructed and utilized to classify pavement surface distresses. The last model, is a next step towards autonomously distinguishing the classified distress with its severity ranking. A Deep Neural Network (DNN) called EnDec (Encoder & Decoder) architecture was built and trained on the Dutch supercomputer called "cartesius", by utilizing multi-threading opportunities, to objectively segment the given pavement surface distress.

This report details the design of an instrumentation system to be used on a skeleton sled. The system will measure data during the run on a skeleton track using several sensors and process and visualise the data afterwards in order to shorten the learning curve of the athlete and give quantitative feedback. The subsystem discussed in this report concerns the measurement of the forces between the body and the sled in order to analyse the steering behaviour of the athlete. This is accomplished via thin film resistive force transducers. The g-forces on the athlete and the sled and the orientation of the sled are measured as well in order to give a better insight how this influences steering and is measured using an IMU (Inertial Measurement Unit). The data is collected using an ESP32 microprocessor.

The costs and damages that result from cyber security weaknesses are increasing year by year. The cybercrime economy has grown to acquire $600 billion in profits every year, nearly one percent of the global GDP according to a study made by The Center for Strategic and International Studies (CSIS), in collaboration with McAfee. This is likely to increase in the upcoming years especially with the growing IoT and smart devices market, mainly because security is often (partially) ignored during the design phase due to its additional costs. As a result, devices become vulnerable to attacks. In 2017, Accenture, a consulting services company, analyzed the security of 30 mobile banking applications and found out that all apps contained at least one known security vulnerability.

For many years there have been advances in software security. It gets harder and harder to attack software, due to many countermeasures developed over the years. As a result, attackers have shifted their focus to hardware attacks. Exploitable vulnerabilities found in hardware most often require hardware revisions. In contrast to software which can be updated easily. There are many forms of hardware attacks; examples are IP piracy, hardware Trojan, side-channel analysis and fault injection (FI). Recent advances in these attacks made some of them accessible to the public, which worsens the problem. One of the popular hardware attacks is FI, which is able to temporarily alter the functionality of the hardware during run time.

This thesis will focus on analyzing the resilience of smartphones against FI attacks, to further improve the security of smartphones, by researching the possibility of using FI to brute force the lock screen of an Android phone. The attack target is a high frequency package on package chip that has not been attacked before in the literature as far as we know. Based on the target design ad properties of the available FI techniques, electromagnetic fault injection (EMFI) was chosen. Using this technique, a characterization of the target chip was performed to verify its vulnerability to EMFI. To be able to use the acquired knowledge from the characterization a FI model was made, i.e., this model is based on the activity during a glitch and the glitch location. The FI model describes that faults can be injected during the transfer of instructions from the DRAM to the cache. A second characterization was performed using the FI model while running the Android OS, which showed that Android doesn't have any defenses against FI. Before attacking the lock screen, a simulation of the attack was performed, which proved the possibility of successfully performing this attack. Unfortunately, the right time to successfully glitch the lock screen was not found due to the large search space, unreliable trigger and possibly the usage of a non-optimal probe position on top of the chip. Nevertheless, it was demonstrated that the lock screen can be attacked by simulating the effect of glitching certain specific instructions and it was proven that PoP chips with a high clock frequency are vulnerable to EMFI.