Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology, we accelerate the development of 300 mm epitaxial wafers manufactured in an industrial CMOS fab and report a remarkable electron mobility of (3.9 ± 0.6) × 10⁵ cm²/Vs and percolation density of (6.9 ± 0.4) × 10¹⁰ cm⁻², representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information, and because of the simplicity of assembly and versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.

Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 10⁵ cm² V⁻¹ s⁻¹) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 10¹¹cm⁻², light effective mass (0.09m_e), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a ²⁸ Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

We report density-dependent effective hole mass measurements in undoped germanium quantum wells. We are able to span a large range of densities (2.0-11×1011cm-2) in top-gated field effect transistors by positioning the strained buried Ge channel at different depths of 12 and 44 nm from the surface. From the thermal damping of the amplitude of Shubnikov-de Haas oscillations, we measure a light mass of 0.061me at a density of 2.2×1011cm-2. We confirm the theoretically predicted dependence of increasing mass with density and by extrapolation we find an effective mass of ∼0.05me at zero density, the lightest effective mass for a planar platform that demonstrated spin qubits in quantum dots.

Superconductors and semiconductors are crucial platforms in the field of quantum computing. They can be combined to hybrids, bringing together physical properties that enable the discovery of new emergent phenomena and provide novel strategies for quantum control. The involved semiconductor materials, however, suffer from disorder, hyperfine interactions or lack of planar technology. Here we realise an approach that overcomes these issues altogether and integrate gate-defined quantum dots and superconductivity into germanium heterostructures. In our system, heavy holes with mobilities exceeding 500,000 cm² (Vs)⁻¹ are confined in shallow quantum wells that are directly contacted by annealed aluminium leads. We observe proximity-induced superconductivity in the quantum well and demonstrate electric gate-control of the supercurrent. Germanium therefore has great promise for fast and coherent quantum hardware and, being compatible with standard manufacturing, could become a leading material for quantum information processing.

Improvement of the photoluminescence (PL) of Phosphorus (P) doped Ge by P atomic layer doping (ALD) is investigated. Fifty P delta layers of 8 ×10¹³ cm^-2 separated by 4 nm Ge spacer are selectively deposited at 300 °C on a 700 nm thick P-doped Ge buffer layer of 1.4 × 10¹⁹ cm^-3 on SiO₂ structured Si (100) substrate. A high P concentration region of 1.6 × 10²⁰ cm^-3 with abrupt P delta profiles is formed by the P-ALD process. Compared to the P-doped Ge buffer layer, a reduced PL intensity is observed, which might be caused by a higher density of point defects in the P delta doped Ge layer. The peak position is shifted by ∼0.1 eV towards lower energy, indicating an increased active carrier concentration in the P-delta doped Ge layer. By introducing annealing at 400 °C to 500 °C after each Ge spacer deposition, P desorption and diffusion is observed resulting in relatively uniform P profiles of ∼2 × 10¹⁹ cm^-3. Increased PL intensity and red shift of the PL peak are observed due to improved crystallinity and higher active P concentration.