This thesis details the design of a high-speed RF delay locked loop(DLL). A new proposed phase detector architecture, coined the mixing phase detector, allows for phase detection at high frequencies, resulting in multiphase generation at these higher frequencies with a DLL. The mixing phase detector modulates the high frequency signal to DC, allowing for elementary circuits to be used that do not need high frequency capabilities. The mixing phase detector has been designed, entirely laid out, and will be taped out shortly, with which simulations have been performed and have been compared with the state-of-the-art. The simulated results, show the possibility of generating eight phases accurately at 11.1 GHz, which would be higher than the state-of-the-art.

Radar technology requires high efficiency and wide bandwidth performance at high output powers. However, new developments like using Joint Communication and Radar Sensing (JCRS), pulse shaping, and amplitude tapering provides an additional requirement: amplitude modulation. To satisfy all of these requirements, a Load-Modulated Balanced Amplifier (LMBA) using a wideband Class E is designed for 2.9-3.4 GHz using GaN transistors. First, an accurate linear model for the transistor is presented. After this, a new state-space solution for a Class-E LMBA is derived. And lastly, a LMBA using a wideband Class E is presented. Using a lossless matching network, the GaN-based amplifier has an average drain efficiency of 81 % over the full 10 dB power back-off. However, the final design has an average drain efficiency of 45 % with a peak output power of 44 dBm.

Autonomous driving can bring revolutionary advancements in transportation, by making vehicles navigate and operate independently without human intervention. To achieve this, autonomous vehicles are equipped with sensors, including cameras, Light Detection and Ranging (LiDAR), and radar, which provide them with a comprehensive view of their surroundings. Frequency-Modulated Continuous Wave (FMCW) radar is the most popular radar sensor employed on autonomous vehicles (AVs), for its long working distance, simultaneous accurate measurements of range and radial velocity of the target, and its robustness for all weather conditions. However, there are still many problems to be solved for FMCW radar for detecting vulnerable road users (VRUs), such as pedestrians. The Constant False Alarm Rate (CFAR) detector plays a crucial role in FMCW radar signal processing, for its adaptive capability to estimate multiple potential targets versus variable clutter and noise backgrounds, and it is often the first step of processing in many automotive radar pipelines.
There have been several published methods for detecting pedestrians. However, most methods hardly consider public real-world radar datasets for their performance evaluation. Meanwhile, conventional CFAR used in autonomous driving, such as Cell averaging CFAR (CA-CFAR) and Ordered-statistic CFAR (OS-CFAR) are not specially designed for Doppler-spread targets (DSTs), while pedestrians are typical DSTs which shows Doppler extension in range-Doppler-map (RDM). This is due to the movement of the arms and legs of pedestrians that make them not only extended targets at mm-wave frequencies but also present a spread Doppler signature.
Therefore, in this thesis a proposed CFAR detector for DSTs enhances the probability of detection compared to two-dimensional (2D) CA-CFAR and two-dimensional (2D) OS-CFAR. The parametric study is conducted on CA-CFAR and OS-CFAR detectors. Additionally, the computation time is reduced dramatically.

In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is f_start=6.65 GHz and f_stop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the f_corner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.

In recent years, short-range reliable wireless system with high data rate and low power consumption has drawn sufficient attention and is in great demand in various applications. For biomedical implantable applications such as neural sensing and Brain-computer Interfaces (BCIs), due to the increasing number of sensing channels and elements, not only the precision of the biomedical analysis is increased, but also a wireless system with higher data rate is required. Besides the high data throughput, as an implanted device, settling within a human or animal body requires high reliability and low power consumption. Such a wireless system finds its position in smart wearable devices as well. With a higher data rate and small form factor, more functionalities can be adapted to those smart wearable devices. The energy-efficient characteristic also allows a longer working time and battery life. Similarly, the above-mentioned wireless system is a prime candidate for multi-media applications like virtual reality (VR). A higher data rate means more visual, audio, and sensing data can be transmitted simultaneously, which allows for more advanced functions and a better user experience. Furthermore, this high data rate, low-power wireless system can be also adopted at advanced control system.
Among all possible technologies, Impulse Radio Ultra-Wide-Band (IR-UWB) technology is a promising solution for this short-range wireless system. Within this master thesis project, a transceiver exploiting IR-UWB technology is proposed and implemented as a solution for the above-mentioned short-range, high data-rate, low-power reliable wireless system. The transmitter is from Yu Huang’s hybrid modulation transmitter. A fifth-order wide-band low-power GM-C low-pass filter is implemented with novel closed-loop GM-C BiQuad architecture in the receiver. Besides, the adoption of Electrical Balanced Duplexer (EBD) and Digital Self-interference Cancellation (DSIC) promises strong isolation between transmitter and receiver. Thus, this transceiver is also full-duplex (FD) and achieves simultaneous radar and communication (RadCom). With RadCom, this transceiver accomplishes a higher integration level, higher spectral efficiency, and lower cost. Besides, it enables a newrange of applications since it can serve as a radar and communication device simultaneously. With the ability of ranging, object detection, and tracking, this transceiver is also an excellent solution for automotive sensing and human sensing: social distancing, child presence detection, non-contact vital sign detection, etc.
Designed and fabricated in TSMC 28 nm CMOS process, this chip has a form factor of only 0.155 mm2. The achieved maximum data rate is 1.66 Gbps, while the transceiver DC power is within 20 mW.

In recent years, the demand for wireless communication devices is rapidly increasing and it is estimated to keep growing exponentially over the coming decade. This demand is accompanied by a demand for high-speed and reliable communication. One of the challenges faced by the RF design engineers is to fulfill these demands while utilizing the limited resource of the frequency spectrum to its full potential. High-bandwidth, multi-channel communication protocols are often used to address these requirements. Over the past decade, digital intensive transmitters are gaining popularity because of their suitability to be used with such protocols. This project addresses a requirement of a highly linear direct digital to RF modulator (DDRM) which fulfills the stringent adjacent channel leakage ratio (ACLR) and in-band linearity requirements of the modern communication standards. The main goal of this project is to design a low-power, highly linear DDRM with high modulation bandwidth that can provide an accurate reference signal to a high-power counterpart. This project presents a 2x11-bit, 4GHz digital-intensive I/Q interleaving DDRM with peak output power equal to 2dBm and maximum modulation bandwidth of 400MHz. The DDRM features a second order hold (SOH) interpolation filtering, digital pre-distortion-like unit cell configuration and complete digital CMOS based I/Q interleaving and mixing. The simulation results indicate that the DDRM achieves spurious free dynamic range lower than -50dBc in a 3.5GHz-4.5GHz band. Also the harmonic distortion (HD), intermodulation product (IM), counter-intermodulation (C-IM) products remain below -50dBc for a tone frequency of 400MHz. The entire design consumes 234mW of power. An additional harmonic rejection technique is evaluated which improves C-IM by 3dB-12dB.

A switched-capacitor power amplifier (SCPA) is a very desirable solution to the problem of enabling amplitude modulation while utilizing high-efficiency switching PA topologies for non-constant envelope wireless RF signals, due to its highly linear AM curve, low complexity, and high scalability. However, drawbacks exist in the form of low efficiency at lower input amplitude levels and strong harmonic distortion. In this master thesis, an SCPA is designed in an advanced technology node for wireless signal transmission. Special considerations are taken to explicitly suppress the harmonics of second and third order by manipulating multiple waveforms. A feedback loop is designed in order to facilitate proper suppression in the presence of variations. The issue of power back-off efficiency is addressed through the method of impedance matching utilized. The system operates between the frequencies of 2.4 GHz and 2.5 GHz. For a carrier frequency of 2.4GHz, a peak system efficiency of 42.75% and a -6dB back-off system efficiency of 22.52% are achieved. The system presents high AM curve linearity with an IIP3 of 42.3 dB. Second- and third-order harmonics remain well below the specification of -41 dBm in all process corners, provided that proper tuning is performed.

In recent years, implantable neural sensing and Brain-computer Interfaces (BCIs)
have manifested their potential in medical and clinical uses. However, their wide adoptions are impractical without reliable wireless telemetry systems for transmitting recorded neuron activities to external devices.

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at backed-off power levels. Currently, PAs are mostly of classes A and B. Both of these are linear, but peak efficiencies are only 50% and 78% respectively. This thesis focuses on implementing Continuous Class F (CCF) PA for WiFi 802.11n over the bandwidth 2.1 - 2.7 GHz, which meets the requirement of high efficiency and good linearity even at backed-off power levels. The CCF PA overcomes Class F’s disadvantage of limited bandwidth as well as maintains peak efficiency of 90.7% over the entire bandwidth. The designed PA has four main blocks: the driver, inter-stage matching, output network, and output stage. The procedure to implement each of these blocks is explained extensively in chapters 3, 4, 5, and 6. The layout of the chip is carried out in TSMC 40 nm, and the chip size is 1.4 mm2. From simulations, the CCF PA has a maximum efficiency of 30 % and EVM of -25 dB at 3 dB back-off across the bandwidth 2.1 -2.7 GHz. The tapeout of the chip is planned in March 2021. Later, the chip can be tested and simulation results will be validated. To the best knowledge of the author, this is the first CCF chip at 2.4 GHz band.

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.

This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered.
The circuits designed are two baseband amplifiers, an intermediate frequency amplifier, a low noise amplifier and an RF power amplifier. The baseband amplifiers are implemented with a Darlington pair in common-collector configuration to achieve a high input resistance, low output resistance, and unity gain transfer.
The intermediate frequency amplifier is centered at 9.95 MHz with a -3dB bandwidth of 2 MHz. The maximum gain is 40.5 dB and can be lowered with up to 39.7 dB using a potentiometer, based on the emitter degeneration principle.
The low noise amplifier has a maximum noise figure of 1.4 dB over the RF carrier band of 88 to 108 MHz. It has a gain of 33 dB, and reaches its 1 dB compression point for an input of -33 dBm. The total harmonic distortion is less than 0.3%.
A class E power amplifier is designed with an efficiency of 72.9%, a transmit power of 3.1 W, and a gain of 31.8 dB.
Furthermore, this reports also presents a systematic design approach for amplifiers, which illustrate the core principles on which all the designs are based.

This thesis presents two submodules which are part of 'an FM Chirp Waveform Generator and Detector for Radar', namely the mixer and the modulator. The goal of this project is to design and simulate these submodules from an educational perspective. The modulator is implemented as a single-ended common-base Colpitts oscillator with modulation capabilities added by means of varactor diodes. The carrier frequency of the presented modulator is tunable from 88 MHz to 108 MHz and the achieved modulation linearity for a sawtooth baseband signal is approximately 34 dB over the tuning range. The presented mixer consist of a double-balanced Gilbert-type topology with 29.5 dB (tunable) gain, 23 mW power consumption, high Input-Output isolation and single-ended output achieved by means of an active load. The project was carried out in the scope of the bachelor graduation project in the bachelor of electrical engineering at the Delft University of Technology.

The "FM Chirp Waveform Generator and Detector for Radar" is a Bachelor graduation project with an educational purpose. In this thesis, two modules of the whole system are designed and simulated. In particular, the sawtooth generator and the FM detector. The sawtooth generator is used to generate a linearly increasing signal, which can be used to make a chirp signal. The FM detector is used to extract the original information signal from the received FM signal. The used procedure consisted of determining possible implementations, setting up the design equations, choosing component values and simulating the circuits in ADS. The sawtooth generator was implemented using a ramp generator, Schmitt trigger and a voltage clamper while the FM detector was implemented using a balanced slope detector and a differential-to-single-ended converter. The results showed that the sawtooth generator can successfully produce a sawtooth waveform and that the FM detector can successfully retrieve it. It was concluded that both the modules satisfy all the requirements, meaning that they should work as expected in the whole system. Finally, the future steps were listed which, among others, include improving the linearity of the sawtooth generator and the FM detector.

In this bachelor thesis the design process of the audio and intermediate frequency amplifiers for a wireless FM tranceiver is documented and explained. The project was done using only descrete components for educational purposes.

This report details the design and implementation of subsystems within a wireless FM transceiver. All the subsystems will be developed and integrated into a working FM transceiver. The subsystems discussed in this report are the modulator and demodulator. The modulator, on the transmitter side, varies the carrier wave frequency, based on the input audio signal. The demodulator, on the receiver side, can detect these variations and retrieve the audio signal. The modulator is implemented using a voltage controlled oscillator, which is based on the Colpitts oscillator. The input audio signal controls the oscillation frequency by modulating varicaps. The demodulator consists of mixer, amplifier and a slope detector. The amplifier is not discussed in this thesis. The mixer uses a local oscillator to shift the RF input signal to an intermediate frequency. This thesis proposes a mixer integrated into a local oscillator, using only one transistor. The detector is based on a slope detector, which differentiates the FM signal and converts it into an AM signal. The differentiator is implemented using a bandpass filter. The audio signal is retrieved from the AM signal using an envelope detector. The work will be concluded with a display of the complete FM transceiver circuit.

This thesis explains the design process of two subsystems of a radio transmitter and receiver. The goal of the project is to transmit audio over a distance using FM modulation. This report will focus on the power amplifier leading to the transmitting antenna and the low noise amplifier connected to the receiving antenna. A design process for a class E power amplifier and a low noise amplifier will be discussed.

Analog-to-digital converters are important blocks in any electronic system which act as a bridge between analog signals and digital processors. The conventional SAR ADC employs a binary search algorithm and has emerged as the most suitable solution for low-power applications, due to its excellent power efficiency. The proposed ADC architecture incorporates a new design approach which combines the high resolution capabilities of oversampled ADCs with a 5-bit configuration asynchronous SAR ADC. In this thesis, the theory, analysis and design of a 2nd order error feedback noise shaping SAR are addressed. The underlying concept of the error feedback topology is to optimize the location of complex zeros in the noise transfer function and improve the SQNR for a lower sampling frequency. The stringent power and area budget imposes challenges in designing active blocks with a low transistor count. The impact of a new switching scheme for the capacitive DAC is examined analytically while considering the trade-off between linearity and power savings. The design uses a small assisting SAR and reaches 96% improvement in power consumption due to switching when comparing to a conventional scheme. The converter operates at 1 MHz and consumes 11 $\mu$W, from a 1.8 V supply. In a bandwidth of 20 kHz and an OSR of 25, it achieves an SNDR of 71 dB, an ENOB of 11.5 bits and a Walden FOM of 98 fJ/conversion-step.