This thesis presents the design, implementation, and evaluation of the RF (Radio Frequency) section of an Open-Hardware Vector Network Analyzer (VNA) intended for quantum research applications. The project aims to create a cost-effective, modular VNA system that fulfills the functional requirements necessary for qubit readout and other quantum measurements.
In the initial chapters, the overall architecture of the VNA is outlined, with specific attention to the power budget and system requirements. The RF generation principles are examined, and a range of RF generators are tested to ensure they meet the signal quality standards, such as spurious emissions and harmonic content. The performance of various RF mixers is also evaluated and found to be sufficient for the RF system.
Experimental results demonstrate the system’s capability to measure the S21 parameter of a resonator cavity, comparable to commercial VNAs. This validates that the RF system meets the specified requirements and can be effectively used in quantum research.
Future work suggested includes the measurement of generator frequency/phase stability over time and exploring the feasibility of implementing power sweeps to enhance the system’s functionality. The findings of this thesis contribute to the development of accessible and flexible tools for quantum technology research, promoting further advancements in the field.

The focus of this report is the design and implementation of a universal gate driver for half-bridge circuits. This design includes a programmable dead-time controller and adjustable properties to ensure efficient and reliable switching on a variety of high-voltage applications. Furthermore, this work includes a comparative understanding of all design choices, such as the options considered for the dead-time controller, the gate driver component and the circuit of the output phase. The designed system is expected to receive as input a PWM signal and generate two output signals to drive a halfbridge configuration. The output pulses must be generated with a programmable dead-time and at the input switching frequency. The end product of this design will be used in the TU Delft Power Electronics Lab. The specific requirements are determined in order to meet the lab’s needs and this report further describes the process from acquiring the technical requirements, the circuit design, and finally, the prototype evaluation.

As the world is getting used to 5G technology, 6G is already on the horizon. With the ultimate goal of very low latency communication and Tbps data rates, 6G supports new wireless technologies such as virtual and augmented reality and autonomous driving. In this new generation of wireless communication, high frequencies up to 100 GHz are used which causes antenna arrays to shrink to the size of a post stamp. Antenna-in-Package (AiP) is an emerging technology that integrates these antennas directly in the packaging material of IC’s. This brings the benefit of high level of integration, making beamforming IC’s an all in one system for communications. Despite this, high integration also comes with challenges. These small antenna systems generate heat on a small footprint which emphasizes the need for a low-loss, efficient system. Moreover, free-space path loss is proportional to frequency so high radiated power is needed, further emphasizing the need for improved efficiency. Lastly, space inside the IC and package material is limited which requires compact solutions for the system’s components. Literature has shown that PA-antenna co-design can reduce losses at the PA-antenna interface by matching the antenna impedance to the impedance of the power amplifier, omitting the need for lossy impedance matching networks. This method, called direct impedance matching, has shown to improve power added efficiency (PAE) in antenna systems with single radiating elements and fixed linear arrays. Nevertheless, the advantage of direct impedance matching has not yet been demonstrated for phased array antennas with active beam forming/steering.

This work demonstrates a novel analysis of PA-antenna co-design at 96 GHz using a 8x8 cavity-backed dual-polarized pin-fed stacked patch array. Two versions of this antenna array are designed in Ansys HFSS, one with an antenna impedance of 50 Ω, the benchmark, and one with a lower impedance of 25 Ω. Both designs are made on a custom package laminate stack-up and are compatible with pin-fed AiP technology. Using Keysight ADS, the antenna designs are co-simulated with an RF front-end circuit comprised of a single tone AC signal, ideal 1-64 channel power divider, ideal continuous phase shifters and realistic SiGe Class A cascode power amplifiers. In this setup, the 50 Ω reference antenna is connected to the PA’s with a matching network in between. Because the 25 Ω antenna array matches the optimal output impedance of the PA, it is directly connected. The performance of both antenna arrays are compared, with the focus on PAE and radiation characteristics. The results show that by going for a directly matched antenna the PAE of the system increases by 15.6% for a broadside beam and 30.4% with a scanned beam (θ = 45◦, φ = 45◦). EIRP for broadside and scanned beams increased from 50.3 W to 56.3 W and from 31.1 W to 37.9 W respectively. Bandwidth, gain, radiation efficiency and side-lobe levels were similar in both arrays but the 25 Ω antenna had 4 dB higher levels of cross-polarized radiation and a 4 dB stronger back-lobe behind the antenna. The advantage of higher efficiency and radiated power outweighs these drawbacks and makes direct impedance matching a good design strategy for 6G beamforming AiP technology.

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise filter. Currently, most phase noise filters are based on the charge injection technique, which can only filter the phase noise of the DLL-based DTC.

This thesis presents a new phase noise filter, which can filter both the DLL and PI phase noise. The proposed phase noise filter is inspired by the noise transfer function from the phase detector’s input to the delay locked loop(DLL) output of a type-II DLL, which shows a first-order low-pass transfer function. The noise suppression pole frequency is adjustable and can be modified by changing the
gain of each component in the circuit. In addition, by carefully placing the frequency of the LDO’s pole, second-order noise filtering can be realized.

During design, a 10-bit DTC is constructed first and the proposed filter is placed behind the DTC to verify the effectiveness of the filter. The design achieves the post-layout level. The simulation results show that the DTC’s phase noise drops from 1.099 psrms to 315.9 fsrms with the filter. The area is 695 μm × 693.5 μm. The design consumes 42.3 mW with 1.8V supply in 180nm BCD technology.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.